Differential Clock Receiver to CML on TSMC CLN2P
The Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of appl…
Overview
The Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications requiring CML signal levels on-chip. The Receiver is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, ranging from high speed communication to low power consumer applications.
The Receiver macro is implemented in Analog Bits’proprietary architecture that uses core and IO devices operated at core voltage. In order to minimize noise coupling and maximize ease of use, the Receiver incorporates proprietary ESD structures, which is proven in several generations of processes.
Key features
- Differential clock receiver
- CML differential output to chip core
- Wide Ranges of input frequencies for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
- Programmable termination
- Built-in hysteresis
- Spread Spectrum tracking capability
- Requires no additional on-chip components or band-gaps, minimizing power consumption
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 2nm | N2P | — |
Specifications
Identity
Files
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Provider
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Frequently asked questions about High-Speed I/O Pad IP
What is Differential Clock Receiver to CML on TSMC CLN2P?
Differential Clock Receiver to CML on TSMC CLN2P is a High-Speed IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this High-Speed?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this High-Speed IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.