Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N5 X24, North/South (vertical) poly orientation

The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. Implementing a wide-parallel and clock-forwarded PHY interface, the IP targets advanced 2.5D packaging to take advantage of much finer pitch die-to-die connections in interposer-based technologies, such as TSMC® Chip-on-Wafer-on-Substrate (CoWoS), than traditional flip-chip organic substrates. The High-Bandwidth Interconnect PHY delivers data rates up to 4Gbps per pin in a flexible architecture that includes up to 80 receive and 80 transmit connections per channel and up to 24 channels per PHY with one redundant lane per channel to improve production yield. The HBI PHY IP is compliant with IEEE 1149.1 (JTAG) and 1149.6 (AC JTAG) boundary scan. The built-in self-test (BIST), internal loopback, and external PHY-to-PHY link tests provide on-chip testability and visibility into channel performance.

• Delivers up to 4Gbps per pin with up to bidirectional 2 Tbps/mm of die edge
• High-bandwidth, low-power, low-latency multi-channel PHY in applications requiring connections between dies within a package
• Partitioning a large SoC into multiple smaller SoCs for flexibility in configuration or for improving yield
• Enabling multiple SoCs to be packaged together to create complex subsystems
• Connecting an SoC to smaller dies containing multiple lanes of SerDes or other functions to implement the SoC in a different process node or foundry than that of the smaller dies
• Compliant with Intel Advanced Interface Bus (AIB) v1.1 standard
• Compliant with IEEE 1149.1 (JTAG), 1149.6 (AC JTAG) for easy integration with SoC testability framework
• Compatible with advanced 2.5D packaging solutions