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Vendor:
Synopsys, Inc.
Category:
DDR
DDR4 multiPHY in UMC (28nm)
The Synopsys DDR4 multiPHY is a physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- ch…
Overview
The Synopsys DDR4 multiPHY is a complete physical (PHY) layer IP interface solution for PC/consumer and mobile ASICs, ASSPs, system-on- chip (SoC), and system-in-package applications requiring high-performance DDR4/DDR3/DDR3L/DDR3U/LPDDR2/LPDDR3 SDRAM interfaces operating at up to 2667 Mbps. The Synopsys DDR4 multiPHY is ideal for systems that require high DDR3/4 performance and also may require compatibility with
the latest mobile SDRAMs (LPDDR2 and LPDDR3) for chips targeting multiple applications with varying performance requirements.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR4 multiPHY is provided as a hard DDR PHY that is primarily delivered as GDSII and includes the application-specific I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4 multiPHY. The DDR4 multiPHY includes a DFI 3.1 interface to the memory controller and can be combined with any of Synopsys’ universal memory or protocol controllers for a complete DDR interface solution.
the latest mobile SDRAMs (LPDDR2 and LPDDR3) for chips targeting multiple applications with varying performance requirements.
Optimized for high performance, low latency, low area, low power, and ease of integration, the Synopsys DDR4 multiPHY is provided as a hard DDR PHY that is primarily delivered as GDSII and includes the application-specific I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4 multiPHY. The DDR4 multiPHY includes a DFI 3.1 interface to the memory controller and can be combined with any of Synopsys’ universal memory or protocol controllers for a complete DDR interface solution.
Key features
- Low latency, small area, low power
- Compatible with JEDEC standard DDR4 up to 2667 Mbps
- Compatible with JEDEC standard DDR3 SDRAMs up to 2133 Mbps
- Compatible with JEDEC standard LPDDR2 SDRAMs up to 1066 Mbps
- Compatible with JEDEC standard LPDDR3 SDRAMs up to 2133 Mbps
- DFI 3.1 compliant interface to the memory controller
- Support for 4-bit, 8-bit, 16-bit and 32-bit wide SDRAMs
- Support for SDRAM components soldered directly to PCB
- Support for DDR4 and DDR3 UDIMMs and RDIMMs
- Data path width scales in 8-bit increments from 8 bits to 72 bits
- Support for partially populated interfaces
- Support for 1, 2, 3, or 4 memory ranks
- Support for Shared AC mode that permits one address and command channel to be time division multiplexed between independent data channels
- Capability to be trained for two distinct frequencies to permit fast changes between two frequencies
- Voltage and temperature compensated delay lines used for:
- Support for the PHY to be distributed around a chip
- Support for 28-nm poly orientation rules
- Includes the PHY Utility Block (PUB)
- At-speed loopback testing on both the address and data channels
- MUX-scan ATPG (stuck-at SCAN)
Benefits
- Supports JEDEC standard DDR4, DDR3, DDR3L (1.35V DDR3) , DDR3U (1.25V DDR3), LPDDR2, and LPDDR3 SDRAMs
- High-performance DDR PHY supporting data rates from 0 to 2667 Mbps
- Per-bit deskew for both read and write data paths
- Per-bit deskew for address/command bus when used with LPDDR3 SDRAMs
- Designed for rapid integration with Synopsys Universal Protocol or Memory Controllers for a complete DDR interface solution
- Includes application-specific DDR I/Os including programmable drive strength and On-Die Termination (ODT)
- DFI 3.1 compliant controller interface
Applications
- Data centers (networking and storage)
- Digital home
- Mobile multimedia
- Wireless connectivity
- Digital office
What’s Included?
- Executable .run installation file which includes GDSII, LEF Files, LVS Netlists, .lib/.db Timing Models, Verilog Model, DRC/LVS Log Files, I/O IBIS Model, I/O HSPICE Netlist, Parameterized Verilog top-level PHY netlist files, Sample Verification Environment, PHY Data Book, Physical Implementation Guide, App Notes, Verification Guide, Installation Guide, Implementation Checklist
- The PHY Utility Block includes Verilog Code, Synthesis/STA constraints and scripts, Sample Verification Environment, Data Book
- DDR PHY Compiler
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 28nm | HPC | Available on request |
Specifications
Identity
Part Number
dwc_ddr4_multiphy_umc
Vendor
Synopsys, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY
,
PHY
Standards & Interfaces
Memory
DDR4
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is DDR4 multiPHY in UMC (28nm)?
DDR4 multiPHY in UMC (28nm) is a DDR IP core from Synopsys, Inc. listed on Semi IP Hub. It is listed with support for umc Available on request.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.