How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SMIC
Category:
DDR
DDR3/DDR2/LPDDR2 COMBO Interface
Key features
- DDR3/DDR2/LPDDR2 COMBO interface for DRAM application
- SMIC 40nm Logic Low Leakage Salicide 1.1V/1.8V/2.5V Process
- Cell Size (Width * height) 30um * 280um with DUP stagger bonding pads
- Work IO voltage: 1.2V/1.5V/1.8V
- Programmable driven-strength, programmable ODT,support DDR3-1333,DDR2-1066,LPDDR2-1066
- Suitable for 8 layer application
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 40nm | 40nm 400 nm | Silicon Proven |
Specifications
Identity
Part Number
SP40NLLD2P_MEMIO_COMBO3
Vendor
SMIC
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR2
,
DDR3
Provider
HQ:
China
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Frequently asked questions about DDR Interface IP
What is DDR3/DDR2/LPDDR2 COMBO Interface?
DDR3/DDR2/LPDDR2 COMBO Interface is a DDR IP core from SMIC listed on Semi IP Hub. It is listed with support for smic Silicon Proven.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.