Vendor: Analog Bits Inc. Category: PLL

Core Powered Wide Range Programmable Integer PLL on TSMC CLN5A

The Core Powered Wide Range PLL is easy to integrate, requiring no analog power supply, and can be placed anywhere on a chip.

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TSMC 5nm N5A View all specifications

Overview

The Core Powered Wide Range PLL is easy to integrate, requiring no analog power supply, and can be placed anywhere on a chip.

This Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation. These PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and thick-oxide devices, on a core level power supply.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 7 600 MHz Post-Divide Reference frequency FPFD 7 200 MHz VCO Frequency FVCO 8000 MHz Output Frequency FOUT 7 4000 MHz Lock Time TLOCK 70 µs Reset Time tRESET 1 µs Output Duty Cycle tDO 45 55 % Area A 0.02 sq. mm Total Power IDD 4.6 mA Operational Voltage V 0.675 0.75 0.825 V Operational Temperature TOP -40 25 125 O C Table 1: PLL Operational Range

Key features

  • Entirely core voltage powered, needs no analog supply voltage
  • Electrically Programmable PLL for multiple applications
  • Wide Ranges of Input and Output Frequency for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Small area footprint
  • Low power consumption
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection
  • Designed for AEC-Q100 Automotive Grade 2 operation.

Block Diagram

Core Powered Wide Range Programmable Integer PLL on TSMC CLN5A block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 5nm N5A —

Specifications

Identity

Part Number
Core Powered Wide Range Programmable Integer PLL on TSMC CLN5A
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Analog Bits Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Core Powered Wide Range Programmable Integer PLL on TSMC CLN5A?

Core Powered Wide Range Programmable Integer PLL on TSMC CLN5A is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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