Vendor: Analog Bits Inc. Category: PLL

Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X

The Core Powered Wide Range PLL is easy to integrate, requiring no analog power supply, and can be placed anywhere on a chip.

TSMC 3nm N3P View all specifications

Overview

The Core Powered Wide Range PLL is easy to integrate, requiring no analog power supply, and can be placed anywhere on a chip.

This Wide Range PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation. These PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and thick-oxide devices, on a core level power supply.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 7 600 MHz Post-Divide Reference frequency FPFD 7 200 MHz VCO Frequency FVCO 5000 10000 MHz Output Frequency FOUT 7 5000 MHz Lock Time TLOCK 70 µs Reset Time tRESET 1 µs Output Duty Cycle tDO 47 53 % Area A 0.033 sq. mm Total Power IDD 22 mW Operational Voltage V 0.675 0.75 0.825 V Operational Temperature TOP -40 25 125 O C Table 1: PLL Operational Range

Key features

  • Entirely core voltage powered, needs no analog supply voltage
  • Electrically Programmable PLL for multiple applications
  • Wide Ranges of Input and Output Frequency for diverse clocking needs
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption
  • Excellent jitter performance with optimized noise rejection

Block Diagram

Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 3nm N3P —

Specifications

Identity

Part Number
Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

Analog Bits to Participate in a Customer Test Chip Tapeout on TSMC A14 and Present Papers with Cerebras, Arm and Socionext on Real-Time On-Chip Power Sensing and Delivery at 2026 TSMC Global OIP Ecosystem Events

At TSMC 2026 North America OIP Ecosystem Forum, Analog Bits will showcase new real-time power observability and sensing analog IP in TSMC’s N2P process technology and present a paper with Cerebras; Papers planned with partners at global OIP Ecosystem events to highlight smarter power delivery for scalable SoCs targeting data centers, automotive and more.

Frequently asked questions about PLL IP cores

What is Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X?

Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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