Vendor: Analog Bits Inc. Category: PLL

Automotive Grade 0 – FracN/SSCG PLL on GLOBALFOUNDRIES 40LP-ESF3H-AG0

The Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-inte…

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GlobalFoundries 40nm LP View all specifications

Overview

The Fractional-N PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, and clock tracking for fine tuning on-the-fly. The PLLs are designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory interfaces.

The programmable Fractional-N divider allows the PLL to lock to an incoming clock source and produce an output clock with a non-integer multiplication factor. The generated clock can be locked to the input source yet adjusted to a fine-degree of precision, and may be adjusted on-the-fly to maintain a relatively drifting local clock need. The updatable programmable fractional feedback divider is provided for this purpose. “On the fly” capability means the frequency transition and re-obtaining lock process for small frequency adjustment is glitch free and contains limited frequency over/undershoot.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 10 60 MHz VCO Frequency FVCO 1200 2400 MHz Output Frequency FOUT 20 1200 MHz Output Duty Cycle tDO 45 55 % Total Area A 0.024 sq. mm Total Power IDD 3.6 mA Operational Voltage (Digital) VDIG 0.99 1.1 1.21 V Operational Voltage (Analog) VANA 2.97 3.3 3.63 V Operational Temperature TOP -40C 25 175 C Table 1: PLL Operational Range AEC-Q100 Ready Grades AEC-Q100 Ready Grade Ambient Temperature Junction Temperature 0 -40°C to +150°C -40°C to +175°C Table 2: AEC-Q100 Ready Grades Supported Metal Stacks Stack Option Stack Name 1 5L1x_1T6x_LB 3 5L1x_2T6x_LB 14 5L1x_2T6x_LB14kA Table 3: Supported Metal Stacks

Key features

  • Electrically Programmable PLL for multiple applications including Automotive Grade 0 at 175C operation
  • Ability to generate precise system clocks synchronized to track remote sources
  • Very fine precision: near 1 part per billion resolution
  • Fully integrated 32-bit datapath (8-bit integer plus 24-bit fractional)
  • Implemented with Analog Bits’ proprietary architecture
  • Low power consumption
  • Spread Spectrum tracking capability
  • Requires no additional on-chip components or band-gaps, minimizing power consumption

Block Diagram

Automotive Grade 0 – FracN/SSCG PLL on GLOBALFOUNDRIES 40LP-ESF3H-AG0 block diagram

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 40nm LP —

Specifications

Identity

Part Number
Automotive Grade 0 – FracN/SSCG PLL on GLOBALFOUNDRIES 40LP-ESF3H-AG0
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Analog Bits Inc.

Learn more about PLL IP core

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Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Automotive Grade 0 – FracN/SSCG PLL on GLOBALFOUNDRIES 40LP-ESF3H-AG0?

Automotive Grade 0 – FracN/SSCG PLL on GLOBALFOUNDRIES 40LP-ESF3H-AG0 is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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