IBM 65nm SF 3.3V Power on Reset
The present Power-On-Reset circuit generates system reset pulses (RST) when the 3.3V power supplier is turned on.
- IBM
- 65nm
- LPe
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
IBM 65nm SF 3.3V Power on Reset
The present Power-On-Reset circuit generates system reset pulses (RST) when the 3.3V power supplier is turned on.
Designed for audio clock generation, this PLL integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control …
IBM 65nm 12-Bit 8-Input 1M/200k SAR ADC
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
SMIC 65nm 1.2v/2.5v Spread Spectrum PLL
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 0.18um 11Bit 500Ksps R2R DAC
SMIC18_R2RDAC_04 is a 11Bit 500KHz DAC IP.
SMIC 0.13um 2.4V Power on Reset
The present Power on Reset IP generates system reset signal (POR18, low level reset) when 3.3v power supplier (VIN18) is turned o…
SMIC 0.13um 3.3V-1.8V 360mA Synchronous Buck DC-DC
The IP is a high efficiency, low ripple, current mode buck switching regulator.
Numerically Controlled Oscillator
Numerically Controlled Oscillators (NCO), also called Direct Digital Synthesizers (DDS), offer several advantages over other type…
IBM 65nm LPE 3.3V/1.2V Power On Reset
The present Power-On-Reset circuit generates system reset pulses (RST) when both the 3.3V and 1.2V power suppliers are turned on.
The I65LPEV25_AMP_01 specifies a rail-to-rail voltage reference buffer.
IBM 65nm 10SF Process 24-Bit Stereo Sigma-Delta ADC/DAC
The I65GV25_CODEC_04 integrates: 2-channel 24-bit sigma-delta ADC, 2-channel 24-bit sigma-delta DAC with headphone driver amplifi…
SMIC 65nm LL 3.3V-2.5/1.2V Power Regulator
This IP is a Low-Dropout (LDO) 3.3V to 2.5V and 1.2V power regulator in SMIC 65nm LL 1.2V/2.5V process.
This IP is a programmable Analog PLL suitable for high speed clock generation.
This IP is a programmable Analog PLL suitable for high speed clock generation.
SMIC 65nm 2.5/1.2V 32768Hz Crystal Oscillator
This is a 32768Hz crystal oscillator specifically designed for ultra-low power application.
SMIC 65nm LL 12-Bit 8-Input 1M/200k SAR ADC
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
SMIC 0.13µm 5v-3.3v Power Regulator
This IP is a Low-Dropout (LDO) 5V to 3.3V power regulator in SMIC 0.13μm 3.3V/1.2V Logic process.
This IP is a programmable Analog PLL suitable for high speed clock generation.
MPEG-1/2 – Layer I/II Audio Decoder
The MPEG-1/2 – Layer I/II Audio Decoder (CWda75) is an audio IP core for decoding one audio stream in real-time(1).
90 dB of SNR, 24-bit mono audio ADC, stereo audio DAC with capless headphone driver
Its small silicon area but exhaustive and robust features make shCOD90.RC50 the most competitive solution for your mixed-signal S…