Vendor: SmartDV Category: Bus Fabric

AHB Decoder IIP

AHB Decoder IP core is compliant with AMBA AHB Specification.

Overview

AHB Decoder IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.AHB Decoder IIP is proven in FPGA environment.

AHB Decoder IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with AMBA AHB specification
  • Supports configurable number of AHB Master
  • Supports configurable number of AHB Slave
  • types, burst transfers and response types
  • Support for all the transfer sizes
  • Supports configurable Endianness of the Data bus
  • Supports feature of decoder to decode address from master and to map to the respective slave on the AHB Channel
  • Supports multiplexor to select the read data slaves and to route to respective AHB Master on the bus
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Simple interface allows easy connection to microprocessor/microcontroller devices

Block Diagram

AHB Decoder IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The AHB Decoder is available in Source and netlist products.
  • The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
AHB Decoder IIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about Bus Fabric IP core

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SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about On-Chip Bus IP cores

What is AHB Decoder IIP?

AHB Decoder IIP is a Bus Fabric IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Bus Fabric?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Bus Fabric IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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