Introducing agileSecure anti-tamper security portfolio
Agile Analog’s tamper detection IP is a comprehensive set of sensors and monitors designed to detect a wide variety of physical attacks and side-channel attacks (SCAs). T
Vendor:
Agile Analog
Category:
ADC
8/10-bit Analog-to-Digital Converter
The agileADC Analog-to-Digital Converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS.
Overview
The agileADC Analog-to-Digital Converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 10-bit resolution at sample rates up to 20 MSps. It includes an eight-channel input multiplexor. Some inputs will be buffered inside the ADC, whereas others will bypass the buffer and be connected directly to the ADC to provide full rail-to-rail capability.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.
Key features
- Resolution: 8b, 10b
- Sampling Rate (Fs): 1 Msps to 20Msps
- Input Signal Bandwidth: Fs/2
- SINAD1: Typ 54dB
- SFDR1: Typ -60dBc
- CMRR2: min 65dB
- PSSR1: Typ 30dB
- Monotonic and no missing codes
- Customisable design for simple SoC integration
- Integrated Calibration Mode
Block Diagram
agileADC block diagram
Benefits
- DFT/DFM
- - AMBA-APB Interface to simply test and operation
- - Incorporated Trim and Calibration to facilitate process and/or manufacturing offsets to be adjusted
- - Built-in test mode
- Configurable Inputs
- - Up to 8 input channels
- - Buffer or unbuffered
- - Differential or Single-ended
- - Rail-to-Rail input
Applications
- IoT, Security, Automotive, AI, SoCs, ASICs
What’s Included?
- Datasheet
- Testing and Integration Guide
- Verilog Models
- Floorplan (LEF)
- Timing models (LIB)
- Netlist (CDL)
- Layout (GDS)
- Physical Verification Report
- Design Report
Specifications
Identity
Part Number
agileADC
Vendor
Agile Analog
Type
Silicon IP
Analog
Resolution bits
8 Bit
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
United Kingdom
Learn more about ADC IP core
Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
The complexity of integrated circuit design has expanded a billion-fold since the invention of the first transistor, guided by the famous “Moore’s Law” of semiconductor manufacturing. An important factor to this ever-growing expansion is the development of the digital design flow. A modern digital design consists of several steps, a simplified flow chart is shown below:
Uncertainty-Guided Live Measurement Sequencing for Fast SAR ADC Linearity Testing
This paper introduces a novel closed-loop testing methodology for efficient linearity testing of high-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). Existing test strategies, including histogram-based approaches, sine wave testing, and model-driven reconstruction, often rely on dense data acquisition followed by offline post-processing, which increases overall test time and complexity.
Time Interleaving of Analog to Digital Converters: Calibration Techniques, Limitations & what to look in Time Interleaved ADC IP prior to licensing
Analog to digital converters have three key input ports along with data output ports as per digital resolution requirements. These inputs ports are Analog Signal, Reference and Clock. If we compare across most of the converter architectures then clock frequency is directly related to output data rate and latency of the data conversion.
Three ways of looking at a sigma-delta ADC device
The growing availability of digital ICs like microcontrollers, microprocessors, and field-programmable gate arrays (FPGAs) allows developers to use complex digital processing techniques rather than analog signal conditioning. For this reason, analog-to-digital converters (ADCs) have become a widely-used component in mixed-signal circuits.
Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR
In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.
Frequently asked questions about ADC IP cores
What is 8/10-bit Analog-to-Digital Converter?
8/10-bit Analog-to-Digital Converter is a ADC IP core from Agile Analog listed on Semi IP Hub.
How should engineers evaluate this ADC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.