The analog-to-digital converter is a differential high speed low power IP which uses Successive Approximation Register (SAR) arch…
The analog-to-digital converter is a differential high speed low power IP which uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core internal SAR ADC which consists of sample/hold circuits, a capacitive DAC, a comparator and logic control circuits.
The ADC is designed with high dynamic performance for input signal frequencies up to Nyquist.
It is perfectly suitable for broadband communication applications.
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 28nm | SLP | Available on request |
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Video ADC - 12-bit Successive Approximation Register (SAR) ADC is a ADC IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for globalfoundries Available on request.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.
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