Vendor: Obsidian Technology Category: PLL

600MHz General Purpose PLL

The OT3128rj is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for th…

Overview

The OT3128rj is a flexible clock multiplier PLL function with a wide range of input and output frequencies and is designed for the ams (Austriamicrosystems)  aC18 or  aH18 0.18µ digital or high voltage CMOS processes. The design features an advanced multi-stage balanced VCO for the exceptional cycle to cycle jitter performance.

Key features

  • Wide range M integer divider. (See ot3122 for M, N, and P dividers)
  • 250MHz – 600MHz output frequency range.
  • Comparable frequency range 8MHz – 50MHz.
  • 18pS RMS cycle to cycle jitter at 600MHz.
  • Lock-detect function.
  • Bypass function.
  • Well defined startup behavior.
  • -40°C to 140°C temperature operation.
  • Available divider selection program.
  • Small cell area: 0.04mm2 in 0.18µ CMOS.
  • 2mW typical power dissipation.
  • 1.8V digital and analog supplies.
  • 0.18µ CMOS process compatibility.
  • Only 1.8V transistors are used in the design.
  • Silicon proven.

Block Diagram

Specifications

Identity

Part Number
OT3128rj
Vendor
Obsidian Technology
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

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Frequently asked questions about PLL IP cores

What is 600MHz General Purpose PLL?

600MHz General Purpose PLL is a PLL IP core from Obsidian Technology listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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