4-Phase LC PLL on INTEL 16

The LCPLL (with 4-phase outputs) addresses stringent performance requirements for various low jitter applications, including high-speed serial link and data converter applications. This PLL is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. With all components integrated, jitter performance and standby-power are significantly improved.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 100 MHz VCO Frequency FVCO 12 GHz Output Frequency FOUT 3 GHz Output Duty Cycle tDO 48 52 % Lock Time TLOCK 10 µs Reset Time tRESET 1 µs Area A 0.124 sq. mm Total Power IDD 20 mW Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V O Operational Temperature TOP -40 25 125 C Table 1: PLL Operational Range

• High performance design for meeting low jitter requirements including Ref Clock applications
• Implemented with Analog Bits’ proprietary LC architecture
• Low power consumption
• Integrated power supply regulation for low deterministic jitter
• Spread Spectrum tracking capability
• Excellent jitter performance with optimized noise rejection
• Calibration code and Bandgap voltage observability (for debug)
• Requires no additional on-chip components, minimizing power consumption
• Scan isolation mode