Vendor: Analog Bits Inc. Category: PLL

4-Phase LC PLL on INTEL 16

The LCPLL (with 4-phase outputs) addresses stringent performance requirements for various low jitter applications, including high…

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Overview

The LCPLL (with 4-phase outputs) addresses stringent performance requirements for various low jitter applications, including high-speed serial link and data converter applications. This PLL is designed for digital logic processes and uses robust design techniques to work in noisy SoC environments.

The PLL macro is implemented in Analog Bits’ proprietary architecture that uses core and 1.8V IO devices. With all components integrated, jitter performance and standby-power are significantly improved.

PLL Operational Range Description Symbol Min Typ Max Units Input Frequency FREF 100 MHz VCO Frequency FVCO 12 GHz Output Frequency FOUT 3 GHz Output Duty Cycle tDO 48 52 % Lock Time TLOCK 10 µs Reset Time tRESET 1 µs Area A 0.124 sq. mm Total Power IDD 20 mW Operational Voltage (Digital) VDIG 0.675 0.75 0.825 V Operational Voltage (Analog) VANA 1.62 1.8 1.98 V O Operational Temperature TOP -40 25 125 C Table 1: PLL Operational Range

Key features

  • High performance design for meeting low jitter requirements including Ref Clock applications
  • Implemented with Analog Bits’ proprietary LC architecture
  • Low power consumption
  • Integrated power supply regulation for low deterministic jitter
  • Spread Spectrum tracking capability
  • Excellent jitter performance with optimized noise rejection
  • Calibration code and Bandgap voltage observability (for debug)
  • Requires no additional on-chip components, minimizing power consumption
  • Scan isolation mode

Block Diagram

4-Phase LC PLL on INTEL 16 block diagram

Specifications

Identity

Part Number
4-Phase LC PLL on INTEL 16
Vendor
Analog Bits Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Analog Bits Inc.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 4-Phase LC PLL on INTEL 16?

4-Phase LC PLL on INTEL 16 is a PLL IP core from Analog Bits Inc. listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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