20 to 300 MHz frequency synthesizer

The system generates stable clock signal with frequency from 20 to 300 MHz. The synthesizer is based on an integer Phase Locked Loop (PLL).
Input ckref is connected to reference clock signal with frequency from 8 to 16 MHz. Output pll_clk is signal with desired frequency.

• SilTerra CMOS 0.18 um
• 1V CMOS input logic signal
• Output current digital 3-bit adjustment (from 0.75 mA to 6.5 mA)
• 1.6 Gbps (DDR MODE) switching rates for transmitter
• Low power dissipation (1.4 mW) for receiver
• Low power dissipation (16.56 mW) for transmitter
• Conforms to TIA/EIA-644 LVDS standards
• Military temperature range: from -60 °C to + 125 °C
• Propagation delay 590ps for transmitter
• Propagation delay 500ps for receiver
• Internal current digital 3-bit adjustment (high inner current for high frequency, from 40 to 300 uA) for receiver
• Portable to other technologies (upon request)

• Data receiving/transmitting systems
• Clock signal generator
• Testing equipment

• Schematic or NetList
• Abstract model (.lef and .lib files)
• Layout view (optional)
• Behavioral model (Verilog)
• Extracted view (optional)
• GDSII
• DRC, LVS, antenna report
• Test bench with saved configurations (optional)
• Documentation