Vendor: M31 Technology Corp. Category: PLL

10~240MHz in, 1.5GHz, Integer PLL, TSMC 28HPC+, N/S orientation

Low Power Fractional PLL is a general purpose frequency synthesizer with an input reference frequency range from 10 to 240 MHz an…

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TSMC 28nm HPC+ View all specifications

Overview

Low Power Fractional PLL is a general purpose frequency synthesizer with an input reference frequency range from 10 to 240 MHz and 3:1 output frequency range. The PLL core is a typical Type-II PLL and the fractional portion of the output frequency is achieved by using a programmable 3rd-ord sigma delta modulator. The PLL core operates on IO supply voltage for excellent supply rejection in noisy SoC applications. It is designed for easy usage and simple integration, eliminating the need for complex configurations.

Key features

  • Supports wide input frequency range: 10MHz to 240MHz
  • Supports 3:1 output frequency range allows optimization for power and jitter performance
  • 24-bit fractional accuracy
  • Supports Spread Spectrum Clocking
  • Lock Detect Signal indicates when frequency lock is achieved
  • Embedded frequency meter circuit for mass production testing
  • Embedded continuous monitoring watchdog circuit for automotive applications
  • Output mux for bypass mode
  • PLL Core Area less than 100µm x 100µm @22nm
  • Low Power Consumption, less than 1.0mA from IO voltage domain at lowest output frequency operation

Block Diagram

10~240MHz in, 1.5GHz, Integer PLL, TSMC 28HPC+, N/S orientation block diagram

Silicon Options

Foundry Node Process Maturity
TSMC 28nm HPC+ —

Specifications

Identity

Part Number
10~240MHz in, 1.5GHz, Integer PLL, TSMC 28HPC+, N/S orientation
Vendor
M31 Technology Corp.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact M31 Technology Corp.

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 10~240MHz in, 1.5GHz, Integer PLL, TSMC 28HPC+, N/S orientation?

10~240MHz in, 1.5GHz, Integer PLL, TSMC 28HPC+, N/S orientation is a PLL IP core from M31 Technology Corp. listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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