Vendor: NTLab Category: PLL

1 – 600 MHz frequency synthesizer

The synthesizer produces stable clock signal in range from 1 to 600MHz.

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TSMC 90nm CIS View all specifications

Overview

The synthesizer produces stable clock signal in range from 1 to 600MHz. PLL with integer factors of the frequency division is used for synthesis.
External reference clock 6 MHz connects with pll_iclk input. The output of the frequency synthesizer forms a stable signal with a frequency from 1 to 600 MHz The range of possible frequencies is set by the dividing ratio control register pll_cfg<9:0> and output frequency is the register value in Mhz. The synthesizer is OFF if value register is 000h.
The device is designed with TSMC CMOS 90 nm technology.

Key features

  • TSMC CMOS 90 nm
  • Reference frequency 6 MHz
  • Output frequency 1 - 600 MHz
  • Supply voltage 1 V
  • Working supply current 1 mA
  • Portable to other technologies (upon request)

Block Diagram

090TSMC_PLL_06 block diagram

Applications

  • Data transmission systems
  • Clock subsystems
  • Measurement equipment

What’s Included?

  • Schematic or NetList
  • Abstract model (.lef and .lib files)
  • Layout view (optional)
  • Behavioral model (Verilog)
  • Extracted view (optional)
  • GDSII
  • DRC, LVS, antenna report
  • Test bench with saved configurations (optional)
  • Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 90nm CIS —

Specifications

Identity

Part Number
090TSMC_PLL_06
Vendor
NTLab
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

NTLab
HQ: Lithuania
Contact NTLab

Learn more about PLL IP core

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Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 1 – 600 MHz frequency synthesizer?

1 – 600 MHz frequency synthesizer is a PLL IP core from NTLab listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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