Vendor: Obsidian Technology Category: PLL

1.2GHz General Purpose PLL for TSMC 0.18u Processes

The OT3124bt is a flexible clock multiplier PLL function with a wide range of input and output frequencies.

Overview

The OT3124bt is a flexible clock multiplier PLL function with a wide range of input and output frequencies. High range M divider allows this PLL to be driven by low power non-overtone crystal oscillator circuits if required. This IP is designed for the TSMC 0.18u digital or mixed signal family of CMOS processes.

Key features

  • Wide range N, M integer dividers.
  • 600MHz – 1.2GHz output frequency range.
  • Comparable frequency range 20MHz – 200MHz.
  • 18pS RMS cycle to cycle jitter at 1.2GHz.
  • Lock-detect function.
  • Bypass function.
  • Well defined startup behavior.
  • -40°C to 140°C temperature operation.
  • Available divider selection program.
  • Small cell area: 0.06mm2 in 0.18µ CMOS.
  • 8mW typical power dissipation.
  • 1.8V digital and analog supplies.
  • 0.18µ CMOS process compatibility.
  • Silicon proven architecture.

Block Diagram

Specifications

Identity

Part Number
OT3124bt
Vendor
Obsidian Technology
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about PLL IP core

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This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

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Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is 1.2GHz General Purpose PLL for TSMC 0.18u Processes?

1.2GHz General Purpose PLL for TSMC 0.18u Processes is a PLL IP core from Obsidian Technology listed on Semi IP Hub.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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