Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfa…
- UCIe
Accelerated confidence in simulation-based verification of RTL designs with Universal Chiplet Interconnect Express (UCIe) interfa…
Industry , AXI5-Stream Solution for UCIe D2D Stacks The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Strea…
The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …
The UCIe Chiplet IP offers a cutting-edge solution for seamless, low-latency data transfer between dies and chips, enabling heter…
Universal Chiplet Interconnect Express(UCIe) VIP
The UCIe VIP , a solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of y…
The Die-to-Die interface is a functional block that provides a data interface between two chip dies within the same package.
UCIe Die-to-Die Chiplet Controller
The UCIe Controller IP is a configurable and customizable UCIe 1.1 compliant die-to-die controller.
UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver.
UCIe based 12-bit 12-Gsps Transceiver (ADC/DAC/PLL/UCIe)
Unleash the power of the new UCIe based RF Chiplet transceiver.
The Die-to-Die interface is a functional block that provides a data interface between two chip dies in the same package.
The ODT-UCIE-UNI-TX-16GXX-16FFCT is a low power D2D transmitter IP in TSMC 16FFC process.
The ODT- UCIE-UNI-RX-16GXX-S8 is a low power D2D receiver IP in Samsung 8nm process.
ForwardEdge’s UCIe IP enables scalable die-to-die connectivity for chiplet-based SoCs.
UCIe Controller add-on CXL2 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller add-on CXL3 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and mai…
Industry , Silicon Proven, 32 Gbps per pin, backed by a portfolio of verification tools, PHY interoperability and integration.
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…
The UCIe Verification IP provides an effective & efficient way to verify the UCIe components of an IP or SoC.