1.8V 2.5MSPS 14-Bit Sigma-Delta ADC - SMIC 55nm
1.8V 2.5MSPS 14-Bit Sigma-Delta ADC - SMIC 55nm
- 14 Bit
- SMIC
- 55nm
- LL
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
1.8V 2.5MSPS 14-Bit Sigma-Delta ADC - SMIC 55nm
1.8V 2.5MSPS 14-Bit Sigma-Delta ADC - SMIC 55nm
7-Channel 22-Bit 9.6KSPS ADC with Internal Reference - SMIC 40nm
7-Channel 22-Bit 9.6KSPS ADC with Internal Reference - SMIC 40nm
7-Channel 16-Bit 9.6KSPS ADC with Internal Reference - SMIC 40nm
7-Channel 16-Bit 9.6KSPS ADC with Internal Reference - SMIC 40nm
16-Bit 100KSPS High Performance ADC - SMIC 40nm
16-Bit 100KSPS High Performance ADC - SMIC 40nm
24-Bit Stereo Audio DAC, SNR>100dB - SMIC 110nm
24-Bit Stereo Audio DAC, SNR>100dB - SMIC 110nm
PUF Hardware Premium with key wrap and certification support
Device identities and cryptographic root keys are at the foundation of every security system.
USB 1.1 Device The USB 1.1 Device IP Core is an USB 1.1 compliant device core with optional AHB, APB, PCI, or Custom bus interfac…
UFS 3.0 is the next specification update pending from JEDEC.
The NAND Flash landscape is changing and the Arasan NAND flash management technology is changing with it.
UFS 3.1 is the next specification update pending from JEDEC.
Serial RapidIO is a communication protocol developed to ensure fast and reliable interconnection between the vendor's boards.
Ethernet IP Core compliant with 100BASE-TX and 1000BASE-T
The Ethernet IP Core is compliant with 100BASE-TX and 1000BASE-T, supporting all commonly used PHY interfaces like MII, GMII, RGM…
The SpaceFibre IP core supports up to 8 lanes.
The NAND memory controller IP core is compliant with the ONFI standard working on asynchronous mode.
The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.
DDR5/DDR4 and LPDDR5/LPDDR4 EMIF FPGA IP
DDR4 and DDR5 offer higher bandwidth and improved performance over previous generations, with DDR5 providing further enhancements…
R-Tile is a FPGA companion tile that supports configurations up to PCIe 5.0 x16 in Endpoint (EP), Root Port (RP), and Transaction…
PCI Express (PCIe*) protocol is a high-performance, scalable, and feature-rich serial protocol with data transfer rates from 2.5 …
Intel® FPGA IP for Ethernet Products Portfolio
Triple Speed Ethernet Triple-Speed Ethernet Intel® FPGA intellectual property (IP) supports the 10 Mbps, 100 Mbps, and 1 Gbps dat…
BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=1.08-1.98V)
The SGC21412 is a versatile and scalable Power Controller for SoC integration.