100G OTN Regenerator/Repeater(OTL4.4)
Aliathon’s 100GE-OTU4 regenerator/ repeater is targeted towards long haul transport in the OTN network.
- Optical Transport
- now
- ITU G.709 compliant
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
100G OTN Regenerator/Repeater(OTL4.4)
Aliathon’s 100GE-OTU4 regenerator/ repeater is targeted towards long haul transport in the OTN network.
Aliathon’s 100G add/drop multiplexor is targeted towards the next generation metro ring topologies for OTN.
Aliathon Ltd.
1.8V Programmable 100MHz Oscillator I/O Pad Set
The Oscillators library provides oscillators for on-chip asynchronous clock generation with an appropriate external crystal.
The Xilinx LogiCORE™ IP Gamma LUT core provides an optimized hardware block for manipulating image data to match response of disp…
The Xilinx LogiCORE™ IP Sensor Demosaic core provides an optimized hardware block that reconstructs sub-sampled color data called…
The Xilinx® LogiCORE™ IP H.264/H.265 Video Codec Unit (VCU) core for Zynq UltraScale+ MPSoC devices is capable of performing vide…
Video Frame Buffer Read and Video Frame Buffer Write
The Xilinx® LogiCORE™ IP Video Frame Buffer Read and Video Frame Buffer Write cores provide high-bandwidth direct memory access b…
Xilinx provides simple clock generator for simulation testbench.
Soft-Decision FEC Integrated Block
For many current and emerging high data rate applications such as 4G, 5G and DOCSIS3.1 Cable Access, transmission reliability is …
Reset Verification IP can be used to generate reset signals in testbench.
Zynq UltraScale+ RFSoC RF Data Converter
The Xilinx® Zynq® UltraScale+™ RFSoC family integrates the key subsystems required to implement a software-defined radio includin…
Thread Synthesis and Reordering attachment IP for use with random access masters to HBM IP
Partial Reconfiguration Bitstream Monitor IP
The Partial Reconfiguration (PR) Bitstream Monitor can be used to identify partial bitstreams as they flow through the design.
Partial Reconfiguration AXI Shutdown Manager IP
The Partial Reconfiguration (PR) AXI Shutdown Manager can be used to make the AXI interfaces between a Reconfigurable Partition a…
QDMA Subsystem for PCI Express
The Xilinx® LogiCORE™ QDMA for PCI Express® (PCIe) implements a high performance, configurable Scatter Gather DMA for use with th…
The LPDDR3 Controller gives you the ability to design with less power and a smaller form factor while maintaining high performanc…
Massive memory bandwidth, the simplicity of an AXI Interface, no need for external pins HBM IP, made available for Virtex UltraSc…
The ETRNIC (Xilinx Embedded Target RDMA enabled NIC) IP is a target only implementation of RDMA over Converged Ethernet (RoCE v2)…
Xilinx Interlaken IP core is based on Sarance Technologies Best-In-Class Intellectual Property Interlaken is a scalable chip-to-c…