The 400G High Speed Ethernet (400G HSEC) Subsystem provides the 400G Ethernet Media Access Control (MAC) with a Physical Coding S…
- Ethernet
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The 400G High Speed Ethernet (400G HSEC) Subsystem provides the 400G Ethernet Media Access Control (MAC) with a Physical Coding S…
The Universal Serial 10GE Media Independent Interface (USXGMII) IP core implements an Ethernet Media Access Controller (MAC) with…
The Polar Encoder/Decoder soft IP core supports Polar encoding and decoding.
Forward Error Correction (FEC) codes such as Low Density Parity Check (LDPC) codes provide a means to control errors in data tran…
The IEEE 802.3 Clause 74 FEC IP core performs the functions of the IEEE Clause 74 FEC, sometimes known as “KR FEC”, as described …
The Xilinx® 10G Ethernet TSN solution provides a 10 Gigabit per second (Gbps) Ethernet Media Access Controller integrated with a …
25G IEEE 802.3by Reed-Solomon Forward Error Correction
Xilinx® offers the 25 Gigabit IEEE 802.3by Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise …
AXI Bus Functional Model (BFM)
The ability to purchase AXI BFM has been discontinued as of December 1, 2016.
Clock Verification IP can be used to generate clock signals in testbench.
ChipScope Pro (IBERT) for Virtex-6 FPGA GTH
The LogiCORE™ ChipScope™ Pro Integrated Bit Error Ratio Tester (IBERT) core for Virtex®-6 FPGA GTH transceivers is a customizable…
The AXI VIP can be used to verify connectivity and basic functionality of AXI masters and AXI slaves with the custom RTL design f…
AXI Stream Verification IP (VIP)
The AXI Stream VIP can be used to verify connectivity and basic functionality of AXI Stream masters and AXI Stream slaves with th…
AXI Sideband Formatter Utility
The Xilinx® LogiCORE™ AXI Sideband Formatter Utility is used to insert and recover sideband information onto the AXI USER signals…
The Xilinx® LogiCORE™ AXI Firewall IP is designed to protect AXI DMA from hangs and protocol violations downstream of it that may…
The Xilinx® LogiCORE™ IP I2S Transmitter and Receiver cores are soft IP cores in Xilinx Vivado design suite which make it easy to…
Converts Avalon Master Endpoints to AXI for seamless interconnection and integration
Xilinx provides an 100M/1G TSN Subsystem to accelerate time to market and drive the convergence of low latency deterministic Indu…
1G/10G/25G Switching Ethernet Subsystem
The 1G and 10G Switching Ethernet Subsystem dynamically switches an Ethernet Media Access Controller (MAC) between 1G or 10G phys…
IP
IP