The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- Controller
- DDR2 + 2
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
The LPDDR5/4/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-packag…
LPDDR5/4/4X PHY - SS 14LPU for Automotive AEC-Q100 Grade 1
The LPDDR5/4/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-packag…
LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X
The LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC st…
LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
The LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC st…
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
LPDDR5X/5/4X PHY - SS 8LPU for Automotive, ASIL B Random, AEC-Q100 Grade 1
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
LPDDR Controller supporting LPDDR5X, LPDDR5, and LPDDR4X
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
LPDDR Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
The LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC s…
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…
The DDR5/4 PHY is a physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring hi…