DDR5 PHY - SS SF2

The DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR5/4 SDRAM interfaces operating at up to 8400 Mbps. The DDR5/4 PHY is ideal for systems that require high-speed, high-performance, and high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 4 physical ranks. Direct SDRAM on PCB systems are also supported.

Optimized for high performance, low latency, low area, low power, and ease of integration, the DDR5/4 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR5/4 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB)that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR5/4 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR5/4 PHY includes a DFI 5.0 interface to the memory controller and can be combined with the DDR5/4 controller for a complete DDR interface solution.

• Supports JEDEC standard DDR5 and DDR4 SDRAMs
• High-performance DDR PHY supporting data rates up to 8400 Mbps
• PHY independent, firmware-based training using an embedded calibration processor
• Supports up to 4 trained states/ frequencies with <3μs switching time
• I/O receiver decision feedback equalization
• VT compensated delay lines for DQS centering, read/write 1D (DDR4) and 2D training (DDR5), and per-bit deskew on both read and write data paths
• DFI 5.0-compliant controller interface
• Designed for rapid integration with Synopsys memory controller for a complete DDR interface solution