UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
- UCIe
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
UCIe-S PHY for Standard Package (x16) in TSMC N5, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A PHY for Advanced Package (x64) in TSMC N5, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x16) in SS SF4X, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A (Gen2) PHY for Advanced Package (x64) in SS SF4X, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x16) in SS SF2, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A PHY for Advanced Package (x64) in SS SF2, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
HBM3 Solution enabling access to HBM3 Controller in TSMC N5 1.2V
The HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard.
HBM3 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N5 1.2V
The HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard.
The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3, DDR3L (1.3…
The Gen 2 DDR multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard LPDDR2, LPDDR3…
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…