High Speed Ethernet 10G to 100G TSN-MAC
The Ethernet 100G MAC IP, compliant with the IEEE802.3/802.3ba standard, implements the full MAC layer and reconciliation sub-lay…
- Ethernet
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
High Speed Ethernet 10G to 100G TSN-MAC
The Ethernet 100G MAC IP, compliant with the IEEE802.3/802.3ba standard, implements the full MAC layer and reconciliation sub-lay…
High Speed Ethernet Quad 10G to 100G PCS
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet Gen-2 Quad 100G PCS IP
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet 4/2/1-Lane 100G PCS
The 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a set of features that enab…
High Speed Ethernet 2/4/8-Lane 200G/400G PCS
The Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a set of fe…
High Speed Ether 2/4/8-Lane 200G/400G/800G PCS
The 800G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the 400G IEEE 802.3bs standard, provides a set of features en…
High Speed Ethernet 200G/400G/800G MAC
The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 s…
High Speed Ethernet 200G/400G MAC
The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 s…
High Speed Ethernet 100G MAC IP
The 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 s…
112G Ethernet PHY, TSMC N5 x4, North/South (vertical) poly orientation
The 112G Ethernet PHY IP, an integral part of the 400GbE/800GbE Ethernet solution enables long reach (LR), medium reach (MR), ver…
1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
The HDCP 2.3 Embedded Security Modules (ESMs) on DisplayPort are autonomous modules that provide designers with a and robust tran…
USB-C 3.1/DisplayPort 1.4 IP Subsystem Solution
Synopsys has pre-integrated USB-C 3.1/DisplayPort 1.4 IP into a single subsystem solution to save customers more than two enginee…
SuperSpeed USB 3.1 Host Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
SuperSpeed USB 3.1 DRD Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
SuperSpeed USB 3.1 Device Controller
The vendor provides designers with silicon-proven, configurable USB 3.1 Controllers.
DisplayPort 1.4 TX PHY, TSMC N5, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for…
Die-to-Die, AIB 2.0 PHY Ported to Intel 16, North/South (vertical) poly orientation
The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
D2D Controller addon for D2D SR112G PHY with CXS interface
The Die-to-Die Controller IP, optimized for latency, bandwidth, power, and area, enables efficient inter-die connectivity in serv…