IPSEC AES-256-GCM (Standalone IPsec)
XIP7213E implements the Internet Protocol Security (IPsec) as standardised in RFC4303 and RFC4305.
- AES
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
IPSEC AES-256-GCM (Standalone IPsec)
XIP7213E implements the Internet Protocol Security (IPsec) as standardised in RFC4303 and RFC4305.
Real-time Pixel Processor for Vision applications
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable Standard Dynamic Range (SDR) capabl…
eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
RapidFlex eFPGA IP provides a reconfigurable, upgradeable, and iterative logic computing layer for SoCs, MCUs, AI accelerators, i…
Microsecond Channel (MSC/MSC-Plus) Controller
The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external…
Silicon agnostic and fully compliant implementation of UALink_200 specification The Chip Interfaces UA Link TL IP Core is a high-…
Silicon agnostic and fully compliant implementation of UALink_200 specification The UA Link DL IP Core is a high-performance, sil…
The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a bus functional model (BFM) with integrated automatic protoco…
Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
High RF performance at the lowest cost The icyTRX-LE-22 RF transceiver PHY IP delivers an optimal trade-off between power consump…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 PHY V2 - TSMC N5A for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 PHY V2 - TSMC N3A for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 PHY V2 - Intel 18A-P
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
Maximum performance for running Linux high-end applications.