MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 12 FFC
C-PHY/D-PHY Combo in various process nodes with low power and cost.
- MIPI D-PHY
- TSMC
- 12nm
- FFC
- In Production
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 12 FFC
C-PHY/D-PHY Combo in various process nodes with low power and cost.
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 7 FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 7 FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.
25MHz Low Jitter XTAL Oscillator with AGC
CT20116 is a crystal oscillator that generates a low jitter 25MHz clock by mean of either an external crystal connected between p…
MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
The D-PHY specification, version 1.2, is fully complied with by the MIPI D-PHY Analog RX IP Core.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 40LP
The MIPI D-PHY Analog TX IP Core fully complies with version 1.2 of the D-PHY specification.
HDMI, LVDS, RF and Analog Pads in TSMC 45/40nm
A 1.0V to 5V Analog I/O library that includes an HDMI, LVDS, and Analog/RF Low Capacitance pad set in TSMC 45/40nm HPM process.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
The MIPI D-PHY RX IP Core fully adheres to the D-PHY specification, version 1.2.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 12FFC
C-PHY/D-PHY Combo in various process nodes with low power and cost.
MIPI D-PHY Rx IP, Silicon Proven in TSMC 7FF
Various manufacturing nodes using C-PHY/D-PHY Combo at minimal cost and power.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes.
USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 55LL
The USB3.1Type-C PHY is a high-speed, SERDES IP with high performance that was created for semiconductors that allow high-bandwid…
eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL
The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption.
Ethernet Real-Time Publish-Subscribe (RTPS) IP Core
The Real-Time Publish-Subscribe (RTPS) core provides a hardware IP solution for the Ethernet RTPS protocol.
USB 2.0 PHY IP, Silicon Proven in TSMC 90G
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 65LP
A physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP.
USB 2.0 PHY IP, Silicon Proven in TSMC 55LP
In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed.
USB 2.0 PHY IP, Silicon Proven in TSMC 12FFC
The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption.
USB 2.0 PHY IP, Silicon Proven in TSMC 7FF
The USB2.0 PHY IP is a full physical layer (PHY) IP solution created for exceptional performance and low power consumption.