32-Bit Automotive Processor - 9-Stage Pipeline, Dual-issue
NA900 series processor is the 1st ISO26262 ASIL-B/D Product Certified RISC-V CPU IP, Nuclei self-developed STL supports multiple …
32-Bit Automotive Processor - 3-Stage Pipeline, Single/Dual-issue
NA300 series processor is a ISO26262 ASIL-B/D Certified RISC-V CPU IP,Nuclei self-developed STL supports multiple ASIL-B automoti…
Nuclei Security processor is a series of chips designed specifically for security application scenarios, including NS100, NS300, …
64-bit High Performance Out-of-Order Processor - Out-of-Order, 3/4/6-Wide Decode
The UX1000 Series have three different variants: UX1030, UX1040 and UX1060.
32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
900 Series processors include four different classes: N900 (32 bit), U900 (32 bit + MMU), NX900 (64 bit) and UX900 (64 bit + MMU).
32-Bit High Efficiency Processor - 3-Stage Pipeline, Single/Dual-issue
N300 Series is a 32-bit RISC-V processor designed for applications requiring extreme energy efficiency and DSP/FPU features.
32-Bit Low Power Processor - 2-Stage Pipeline, Single-issue
N200 Series is designed for deeply embedded application with low power and area consumption.
32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU).
32-Bit High Performance Processor - 2-Stage Pipeline, Single-issue
With extreme low area, N100 is a 32b RISC-V processor designed specifically for low power application.
The RTC (Real Time Clock) provides an automatic wake-up to manage all low-power modes.
The CORDIC IP provides hardware acceleration of mathematical functions (mainly trigonometric ones) commonly used in motor control…
The Fast Fourier Transforms (FFT) are an efficient class of algorithms for digital computation of the Discrete Fourier Transform …
Cryptographic engine using the DES, Triple-DES or AES
The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
Security Hash, SM3 Hash and HMAC Engine
The hash processor is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512), …
On-the-fly decryption engine FRTDEC allows to decrypt on-the-fly AXI traffic based on the read request address information.
Asymmetric cryptographic accelerator
The ACrypto Engine is an asymmetric cryptographic accelerator suitable for embedded application.
PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5…
XEC is a high performance 1000M/100M/10M Ethernet Controller IP.
The DDR PHY IP is a combination of hard macro, I/O Pad and synthesizable RTL to provide a physical interface to JEDEC standard DD…
The DDR controller (DDR4/LPDDR4 Controller) supports the following SDRAM types: DDR4 LPDDR4 On the host side, DDR4/LPDDR4 Control…