Frontgrade Gaisler IP Cores

The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction.

• Spacewire
• Compliant with ECSS-E-ST-50…

The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems.

• Protocol Bridge
• Production
• Immediate
• PCI SIG 2.2

The LEON3 processor offers robust fault tolerance and performance for space and high-reliability applications, including satellit…

• CPU
• Production
• Immediate
• SPARC V8 (IEEE-1754)

The GRETH_GBIT core implements a 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface.

• Ethernet
• Production
• Immediate
• IEEE 802.3

The GRETH is a 10/100 Mbit/s Ethernet MAC controller IP with AMBA host interface The GRETH core implements a 10/100 Mbit/s Ethern…

• Ethernet
• Production
• Immediate

The GRSPW2 core implements a SpaceWire link controller with SpaceWire RMAP support and AMBA host interface.

• Spacewire
• Fully validated on silicon
• Now
• ECSS-E-50-12

The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus.

• SPI / QSPI XSPI

GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation…

• Monitoring

The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard.

• Spacewire
• Compliant with ECSS-E-ST-50…

The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote …

• Mil Std 1553
• Now
• MIL-STD-1553B (Notice 2) da…

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development.

• Bus Fabric
• Production
• Now

GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend.

• CAN / CAN-FD / CAN-XL
• Production
• Now
• CAN 2.0, AMBA 2.0

The SPI to AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal…

• Protocol Bridge

FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.

• DDR

The I²C slave core is a simple I²C slave that provides a link between the I²C bus and the AMBA APB.

• I2C / I3C

The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.

• I2C / I3C

The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB.

• Protocol Bridge

The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.

• USB

The NOEL3 is a configurable RISC-V processor IP core, described in VHDL.

• CPU

Hardware security module IP core with function to support crypto key storage, boot authentication, supervision, and offloading of…

• Root Of Trust