Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+
SP Ultra Low Leakage SRAM.
Overview
SP Ultra Low Leakage SRAM. Only SRAM on market which utilizes L110 Bit Cell together with high Vt Periphery to provide lowest leakage together with highest yield.
| Bit Cell | Power Supply (V) |
| L110 | 0.65/0.8 |
Key features
- Ultra-Low Leakage: High VT (HVT) and low leakage (LLHVT) devices are used with source biasing to minimize standby currents while operating at low voltage
- Bit Cell: Utilizes GlobalFoundries® Ultra-Low Leakage, 6T(L110) bit cells to ensure high manufacturing yields
- Five Power Modes: High Performance, Low Leakage, Standby, Retention, and Power Off modes provide flexibility for power optimization
- Speed Grades: Three options to adjust the speed/leakage balance and optimize for high speed or low power operation
- Memory Ready Output: Create a Pseudo-Dual Port memory utilizing the READY pin
- High-Density Solutions: Abutment capability to enable multi-instance macros
- Data Write-Through: Optionally prevent data out transitions during a write to reduce power
- Error Correction: Optional SECDED logic for single-bit correction and dual bit detection
Block Diagram
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 22nm | FDX+ | — |
Specifications
Identity
Provider
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Frequently asked questions about SRAM IP cores
What is Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+?
Single Port Low Leakage SRAM Memory Compiler on GF 22FDX+ is a SRAM IP core from Nordic Semiconductor Seattle listed on Semi IP Hub. It is listed with support for globalfoundries.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.