Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
Cadence Design Systems, Inc.
Category:
SRAM
Simulation VIP for HyperFlash
Hyperflash in production since 2018 for many production designs.The Cadence® Memory Model Verification IP (VIP) for HyperFlash pr…
Overview
Hyperflash in production since 2018 for many production designs.
The Cadence® Memory Model Verification IP (VIP) for HyperFlash provides verification of HyperFlash Controller using the HyperBus protocol. It provides a mature, highly capable compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for HyperFlash is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Supported specification: Features of Cypress specification Document Number: 001-99198 Rev. *H Revised February 06, 2017.
Key features
- Density
- From 128Mb to 512Mb
- General Functionality
- Supports Status Register Read and Clear commands
- Supports Program, Read commands for POR Timer Register
- Supports Interrupt Control and Status Registers
- Supports Volatile and Non-Volatile Configuration Control Registers
- Read memory array data, Program data into memory, Program data to flash memory
- Supports commands for Erase, Suspend and Resume, Blank check, Enter Deep Power Down
- Support Program buffer to flash confirm command
- Support Device Input and Output timing and Variants memory operations timing
- Burst
- Wrapped burst: Supports burst lengths: 16 bytes (8 clocks), 32 bytes (16 clocks), 64 bytes (32 clocks), linear burst and hybrid burst: One wrapped burst followed by linear burst
- Reset Output Pin Functionality
- Supports Reset functionality through: Hardware Reset (via RESET# pin), Reset and Address Space Overlay (ASO) Exit (0xF0) command, System-level power-on reset via RSTO#
- Interrupt
- Supports INT# output to generate external interrupt during: Busy to Ready Transition and ECC detection
- DDR Center Aligned Read Strobe
- Supports phase shifting of the RWDS signal with respect to the read data outputs using Phase Shifted Clock input PSC and PSC# pins
- ASO Capability
- Command support for for various ASOs such as: ID-CFI, ASPR ASO, Password ASO, PPB ASO, PPB Lock Bit ASO and DYB ASO
- ECC
- ECC Status Enter, ECC Status Read, Error Lower Address Register, Error Upper Address Register, Read Error Detection Counter and Clear ECC Errors
- CRC
- CRC ASO Entry, Load CRC Start/End Address, CRC Suspend, Array Read, CRC Resume, Read Check-Value Low/High Result Register
Block Diagram
Simulation VIP for HyperFlash block diagram
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
Simulation VIP for HyperFlash
Vendor
Cadence Design Systems, Inc.
Provider
Cadence Design Systems, Inc.
HQ:
USA
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Frequently asked questions about SRAM IP cores
What is Simulation VIP for HyperFlash?
Simulation VIP for HyperFlash is a SRAM IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.