Dual Rail SRAM Globalfoundries 22FDX
Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware im…
Overview
Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX® Platform solution. The Racyics® Dual Rail SRAM supports ultra low voltage core logic operation down to 0.4 V while operating dense, low leakage standard bit cells from a 0.8 V memory supply.
Key features
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABX
- Direct interfacing to ULV Racyics® ABX digital standard cell domains without additional level shifters
- Fullset of characterization corners for -40°C to 125°C temperature range for Racyics® ABB aware timing and power sign-off
- Full statistical LVF characterization for low voltage operation
- Production test methodology available for ABB
Block Diagram
What’s Included?
- Verilog simulation models
- .libidb timing (NLDM, CCS, LVF) and power models
- .lef layout abstract views
- Milkyway database
- GOSH layouts
- LVS netlist
Files
Note: some files may require an NDA depending on provider policy.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 22nm | FDX | — |
Specifications
Identity
Provider
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Frequently asked questions about SRAM IP cores
What is Dual Rail SRAM Globalfoundries 22FDX?
Dual Rail SRAM Globalfoundries 22FDX is a SRAM IP core from Racyics GmbH listed on Semi IP Hub. It is listed with support for globalfoundries.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.