Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
Cadence Design Systems, Inc.
Category:
SRAM
Simulation VIP for HyperRam
HyperRam in production since 2018 for many production designs.The Cadence® Memory Model Verification IP (VIP) for HyperRam provid…
Overview
HyperRam in production since 2018 for many production designs.
The Cadence® Memory Model Verification IP (VIP) for HyperRam provides verification of the HyperRam controller using the HyperBus as well as xSPI Interface protocol. It provides a mature, highly capable compliance verification solution applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for HyperRam is compatible with the industry-standard Universal Verification Methodology (UVM), runs on all leading simulators, and leverages the industry-standard Cadence Memory Model core architecture, interface, and use model.
Supported specification: Features of Cypress (Infineon) and Winbond. The Cypress (Infineon) HyperRam device supports both interfaces: HyperBus as well as Octal Interface as HyperRam1.0 and HyperRam2.0 respectively.
Key features
- Density
- From 64Mb to 128Mb
- Reset
- Hardware Reset via RESET# pin
- Read and Write
- Write Enable and Write Disable commands to enable WEL latch for xSPI Octal Interface Support - Cypress HyperRAM 2.0
- Supports Read/Write operation for registers: ID0 and ID1 (Read Only) and CR0/1 (Read/Write)
- For xSPI Octal Interface Support - Cypress HyperRAM 2.0: Read and Write any register and Read ID Select Burst type from CR1[7] bit
- Burst
- Wrapped burst with lengths of 16, 32, 64, and 128 bytes, Linear burst, hybrid burst: One wrapped burst followed by linear burst.
- DCARS
- DDR Center-Aligned Read Strobe Functionality for Cypress
- Extended I/O Support
- Winbond Specific: DQ[15:0] and RWDS[1:0]
- Winbond Specific
- Hybrid Sleep Mode, Partial Array Refresh, Master Clock Type, and Software Reset
- Power Modes and Software Reset
- For xSPI Octal Interface Support - Cypress HyperRAM 2.0, support of Deep Power Down and Software Reset: Reset and Reset Enable
Block Diagram
Simulation VIP for HyperRam block diagram
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Part Number
Simulation VIP for HyperRam
Vendor
Cadence Design Systems, Inc.
Provider
Cadence Design Systems, Inc.
HQ:
USA
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Frequently asked questions about SRAM IP cores
What is Simulation VIP for HyperRam?
Simulation VIP for HyperRam is a SRAM IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.