USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.1 Base Specification with support…
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
For high-bandwidth applications, the PCIe 5.0 PHY IP offers excellent performance, multi-lane capabilities, and low power design.
The Cadence® PIPE PHY Verification IP (VIP) provides a mature, capable verification solution for the PHY layer of complex protoco…
PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP
PCIe Gen 3.1 transmission is supported by (PCIe 3.1) x4 PHY IP.
10Gbps Multi-Protocol PHY IP (+PCIe 3.1)
10G-KR, XFI, PCIe 3.1/2.0/1.0, XAUI, QSGMII, SGMII, Gigabit Ethernet Growing 10 Gigabit Ethernet deployments in the data centers …
GTS is a general purpose transceiver in Agilex™ 5 and Agilex™ 3 FPGAs.
The PCIe Gen 6 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 6 interfa…
The PCIe Gen 5 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 5 interfa…
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5…
The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC an…
The Synopsys Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, a…
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 40LP
Compliance with the PCIe 3.0 Base Specification is standardized by the PCIe 3.0 PHY IP with PIPE 4.3 interface standard.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP
The PCIe 3.0 PHY IP is designed to support increased applications with its low-power, multi-lane, high-performance design.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
High-bandwidth applications can avail advantage of PCIe 3.0 PHY IP's high performance, multi-lane scalability, and low-power layo…
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
To support high-bandwidth applications, PCIe 3.0 PHY IP provides a low-power, multi-lane, high-performance design.
PCIe 3.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
For the high-bandwidth applications, PCIe 3.0 PHY IP offers high-performance, multi-lane capabilities, and low-power design.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
For high-bandwidth applications, the PCIe 4.0 PHY IP delivers high-performance, multi-lane capabilities and a low-power design.
PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm
The high-bandwidth applications benefit from the low power, multi-lane, and high-performance PCIe 4.0 PHY IP's design.
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
With compatibility for PIPE 4.4 interface protocol, this Peripheral Component Interconnect Express (PCIe) x4 PHY complies with PC…
PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
With compliance for PIPE 4.4 interface spec, Peripheral Component Interconnect Express (PCIe) Gen4 PHY IP complies with PCIe 4.0 …