graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
- Controller + PHY + 1
- TSMC
- 6nm
- N6FF
High Bandwidth Memory (HBM) IP encompasses the controller, PHY, and associated interface logic required to connect SoCs, AI accelerators, GPUs, and HPC processors to HBM memory stacks through advanced 2.5D and 3D packaging technologies.
HBM interfaces provide extremely high memory bandwidth through wide parallel buses, multiple independent channels, and low-power signaling. Modern implementations support HBM2E, HBM3, HBM3E, and emerging HBM4 standards, enabling memory subsystems that deliver multi-terabyte-per-second bandwidth while maintaining high energy efficiency.
This catalog includes HBM controllers, PHYs, verification IP, and subsystem solutions designed for advanced-node ASICs targeting AI training and inference, high-performance computing, networking, and data center applications. Solutions can be compared based on supported HBM generation, bandwidth, channel architecture, reliability features, packaging requirements, and foundry process compatibility.
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
HBM2E PHY V2 (Hard 1) - TSMC 7FF18
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
HBM2E PHY V2 (Hard 1) - TSMC 6FF18
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
HBM2E PHY V2 (Hard 1) - TSMC 5FF12
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
HBM3 V2 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N3E
The HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard.
Rambus is offering the industry’s first HBM4 Controller IP core designed to support customers with deploying a new generation of …
The Rambus HBM3E / HBM3 controller cores are designed for use in applications requiring high memory bandwidth and low latency inc…
HBM2/2E Memory Controller Core
The HBM2E memory controller IP is designed for use in applications requiring high memory throughput including performance-intensi…
First to market with multiple early adopters of production designs.This Cadence® Verification IP (VIP) provides support for the H…
In production since 2015 on dozens of production designs.This Cadence® Verification IP (VIP) provides support for the JEDEC® High…
graphics, high-performance computing (HPC) and networking applications are requiring more memory bandwidth to keep pace with the …
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…
HBM3 Solution enabling access to HBM3 Controller in TSMC N5 1.2V
The HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard.
HBM3 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N5 1.2V
The HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard.
The HBM3 PHY is a physical layer IP interface (PHY) solution for high-performance computing (HPC), AI, graphics, and networking A…