HBM3 Solution enabling access to HBM3 Controller in TSMC N5 1.2V

The HBM3 Controller IP is optimized for power, latency, bandwidth, and area, supporting the JEDEC HBM3 standard. The controller interoperates with the HBM3 PHY IP via an extended DFI 5.0 interface to create a complete memory interface solution. The HBM3 controller with pseudo channel support and flexible configuration options enhances memory bandwidth. The Controller includes software configuration registers, which are accessed through the Arm AMBA APB v2.0 specification interface.

The HBM3 Controller includes the advanced dynamic memory access command scheduler (eg. CAM, QoS), memory protocol handler (eg. refresh, refresh management), Power saving capabilities (eg. self-refresh, power down, DFI low power, frequency change), reliability features (Read/Write DQ parity, command access (CA) parity, single error correction—double error detection error correcting code—SEC-DED ECC), PHY management and DRAM maintenance control (controller update, PHY update, controller message) and pseudo-channel support.

• JEDEC HBM 3.0 DRAM
• DFI 5.0 compliant interface to HBM3 PHY
• Multiport Arm® AMBA® interface (4 AXI AXI™) with managed QoS or single-port host interface, per pseudo-channel
• Data rates up to 6.4 Gbps (DFI 1:1:2) (1.6GHz controller clock)
• Up to 32 pseudo channels
• 16 to 64 banks per pseudo channel
• Channel density of 2Gb to 32 Gb
• Multiple stack height support
• SEC-DED ECC
• Data scrubbing
• Autonomous per-bank/all-bank refresh
• Autonomous refresh management
• Periodic management control
• DBIac support
• Dynamic Memory Access Scheduling (CAM Base Scheduling)
• CAM size (32 or 64)
• Read Modify Write (RMW)
• QoS (HPR, VPR, LPR, VPW, NPW)
• Page policy (Open, Close with timer)
• Anti-starvation control
• Address collision control (data coherency)
• Programmable logical to physical address remapping