DDR Interface IP cores provide the controller, PHY, and calibration technologies required to connect SoCs and ASICs to external DRAM memory devices, enabling high-bandwidth and low-latency memory access for compute-intensive applications.
This category includes IP solutions supporting DDR2, DDR3, DDR4, and DDR5 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, training engines, initialization logic, timing management, ECC support, and signal integrity optimization features designed for reliable operation across advanced semiconductor process nodes.
TSMC CLN20SOC 20nm DDR4 PHY - 2933Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN20SOC 20nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLLLVT 16nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLLLVT 16nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLLLVT 16nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLL 16nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLL 16nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN16FFCLL 16nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLLLVT 12nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR4 PHY - 4266Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
TSMC CLN12FFCLL 12nm DDR3 PHY - 2133Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adj…
1 Gbps DDR rail to rail LVDS receiver
LVDS_RX is LVDS receiver with rail to rail input range.
065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmit…
1.6 Gbps DDR Programmable LVDS Transmitter/Receiver
090TSMC_LVDS_02 consists of transmitter (LVDSOUT), receiver (LVDSIN) and a bias.
The DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3 and DDR2 SDRAM memor…
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…