The USB1.1 PHY is an IP version of USB transceiver.
- UCIe 1.1
- SMIC
- 180nm
- G
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The USB1.1 PHY is an IP version of USB transceiver.
SMIC 0.18um Reduced Swing Differential Signaling Transmitter
This is an embedded bus transmitter for RSDS™ (Reduced Swing Differential Signaling) interface.
650M LVDS transmitter, 5 channel
The LVDS transmitter is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
LVDS receiver, 650M, 5 channel
The LVDS Receiver IP is designed to support Single Link transmission between Host and Flat Panel Display with up to SXGA+ resolut…
The USB11PHY is an IP version of USB transceiver.
32:1 serializer followed by sub-LVDS drivers
The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data.
Sub-LVDS receiver followed by 1:4 de-serializer
The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word.
IP
SMIC 130nm G LVDS 800Mbps Transmitter
IP
SMIC 130nm G LVDS 1.25Gbps Transmitter
IP
SMIC 130nm G LVDS 1.25Gbps Receiver
IP
IP
IP
SMIC 130nm G LVDS 800Mbps Receiver
IP
IP
IP
10-bit dual-port 30MHz ~ 85MHz LVDS Tx;
IP
IP