VISENGI's PNG Decoder IP core has been developed to be a standards compliant high speed hardware lossless PNG image decompressor.
- Data Compression
- Implemented into ASIC and FPGA projects
- Production
- PNG specification
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
VISENGI's PNG Decoder IP core has been developed to be a standards compliant high speed hardware lossless PNG image decompressor.
VISENGI's PNG Encoder IP core has been developed to be a standards compliant high speed hardware lossless PNG image compressor.
Revolutionary Quad-Pipelined Ultra High Performance Microcontroller
The DQ8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller, designed to oper…
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium…
TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible TETRA-TEDS error control decoder.
Behavioral knowledge space combination rule core with parallel operation
So_ip_ecr_bks_p core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Behavioral knowledge space combination rule core with serial operation
So_ip_ecr_bks_s core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Weighted majority voting combination rule core with parallel operation
So_ip_ecr_mvt_p core can be used to implement the Weighted Majority Voting combination rule to calculate the ensemble classificat…
Majority voting combination rule core with parallel operation
So_ip_ecr_mv_p core can be used to implement several Majority Voting combination rules to calculate the ensemble classification o…
Majority voting combination rule core with serial operation
So_ip_ecr_mv_s core can be used to implement the several variants of the Majority Voting combination rule to calculate the ensemb…
So_ip_edte_un_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consistin…
Area-efficient decision tree ensemble evaluation core based on serial evaluation of ensemble members
So_ip_edte_un_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consistin…
Decision tree ensemble evaluation core based on parallel evaluation of ensemble members
So_ip_edte_smpl_p core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
Decision tree ensemble evaluation core based on serial evaluation of ensemble members
So_ip_edte_smpl_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consist…
Decision tree ensemble classifier inference core
So_ip_idte core can be used create an ensemble of decision trees directly in hardware.
Decision tree evaluation core using serial architecture
So_ip_edt_un core can be used to implement the decision tree with the previously defined structure directly in hardware.
Decision tree evaluation core using pipelined architecture
So_ip_edt_smpl core can be used to implement the decision tree with the previously defined structure directly in hardware.
Very High Speed 3GPP LTE Turbo Encoder
This is a very high speed 8 state 3GPP LTE compatible parallel concatenated turbo encoder.
High Speed CCSDS Turbo Encoder
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder.
Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
TC2000 is a flexible Viterbi decoder covering LTE, 3GPP WCDMA and WiMAX 16e/m specifications.