Purpose-built AI model compression IP, combining software compression with hardware decompression for static model data and hardw…
- Data Compression
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Purpose-built AI model compression IP, combining software compression with hardware decompression for static model data and hardw…
RISC-V AI Acceleration Platform - Scalable, standards-aligned soft chiplet IP
Unlocking AI with Open Compute Traditional AI processors force customers into closed hardware-software ecosystems that limit inno…
The CCSDS/ECSS Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the sp…
Low-density parity-check (LDPC) codes are linear error correction codes that allow you to transmit messages over noisy channels.
ARC IoT Communications IP Subsystem
IP
LLM Accelerator IP for Multimodal, Agentic Intelligence
HyperThought is a cutting-edge LLM accelerator IP designed to revolutionize AI applications.
Revolutionary vector processor
From early Motorola and TI DSPs to modern smartphone DSPs in application processors, DSPs have been designed and optimized for in…
Crest Factor reduction block minimizes the likelihood that a transmission side Power Amplifier (PA) gets saturated while transmit…
As serial link speeds have increased, the reach achievable has become more and more limited by the lossy nature of the physical m…
Digital PID Controller Loop Algorithms for EMA
We have developed control system algorithm IP blocks to be able to control electromagnetic actuators.
Speedcore embedded FPGA (eFPGA) IP has brought the performance and flexibility of programmable logic to ASICs and SoCs.
Ultra-low-power Processor based on RISC-V Architecture
The icyflex-V processor is a new ultra-low-power core based on the RISC-V 32-bit ISA, a long-awaited addition to the CSEM icyflex…
CCSDS 121/123 Lossless Compression
The GRSHYLOC IP enables lossless compression for multi-spectral and hyper-spectral images according to the CCSDS121 and CCSDS123 …
BCH encoder and decoder for NAND FLASH
This IP is a BCH code encoder and decoder designed for storage application to address the reliability challenges.
The FH-OFDM modem is developed for OFDM applications used in frequency hopping transmission scenarios or fixed frequency scenario…
The NAVIC BCH decoder is developed for satellite navigation applications.
The NR-5G Polar encoder/decoder is developed for 5G new radio.
DVB-S2X Wideband LDPC/ BCH Encoder
The DVB-S2X Wideband LDPC BCH Encoder IP Core is developed for Digital Video Broadcasting applications.
Fixed Point Doppler Channel IP core
The Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase …
(2048,1723) LDPC decoder for IEEE 802.3an 10GBASE-T
The LDPC IP is a specialized encoder and decoder for Low-density parity-check codes, specifically designed for the 802.3an standa…