Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements.
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
The MVD DVB-S core is a drop-in module that includes the following functions: - Input data framer from DVB-SPI source (MPEG-TS fl…
The CMS0025 DVB-S2/S2X Modulator with integrated LDPC encoder has been designed specifically to address the requirements of the E…
24-bit General-purpose Fixed-point DSP Core, ADSP-218X Fully Compatible plus Enhancements
The WSP2416 DSP core is a high-speed scalar (one instruction per clock cycle) 24-bit/16-bit Dual-mode fixed-point Digital Signal …
16-bit General-purpose Fixed-point DSP Core, ADSP-218X Fully Compatible plus Enhancements
The WSP1600 DSP core is a high-speed scalar (one instruction per clock cycle) 16-bit fixed-point Digital Signal Processor optimiz…
High-Speed Turbo Product Code decoder
TC3404 is a 2D TPC decoder that is optimised for high-speed.
Industry reference DVB-RCS turbo decoder
TC1000 implements the turbo code specified by DVB-RCS for Interactive 2-way satellite systems.
5G LDPC Decoder
5G Polar Decoder
4G/5G Dual Mode Cell Search
LTE Turbo Decoder
LTE Viterbi Decoder
High-precision 16-bit complex digital up-converter / IQ modulator (DUC) with a fully configurable interpolation filter stage.
Flash Memory LDPC Decoder IP Core
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps …
ION 64b66b IP (64b/66b High-speed Serial Interface)
High-speed serial interface achieved using a lightweight protocol ION 64b66b is an IP for high-speed serial interface targeting a…
ION 8b10b IP (8b/10b High-speed Serial Interface)
High-speed serial interface achieved using a lightweight protocol ION 8b10b is a high-speed serial interface targeting applicatio…
In the DVB-T2 transmission, the Physical Layer Pipes (PLPs) carries the MPEG-2 Transport Streams (TSs).