Right-Sizing Your Cryptographic Processing Solution
By Synopsys
The cornerstone of all security solutions that deal with confidentiality, integrity and authentication is cryptography. Cryptography is a complex math problem used to help create security applications. Algorithms vary for different applications and are used for specific purposes. The common cryptographic algorithms are symmetric block ciphers for confidentiality, hash functions for integrity, and public key cryptography for authentication. Performance requirements for these operations range widely depending on the specific application and market. Implementation and runtime costs for meeting these requirements vary even widely.
In this white paper we investigate different cryptography implementation options and trade-offs, describe the measurable parameters, and analyze examples. We introduce and use the new EEMBC SecureMark™ benchmark for these measurements. This benchmark was developed under the umbrella of EEMBC by an industry consortium chaired by Synopsys. It provides an accurate, reliable tool to compare the efficiency of cryptography implementations for several security profiles quickly and equitably.
To read the full article, click here
Related Semiconductor IP
- 64-bit, RISC-V, ultra-high performance processors
- 64-bit, RISC-V, performance and data computation processors
- 32-bit, RISC-V, deeply embedded processors
- Verification IP for eUSB 2 v2 and USB 2.0
- AFDX 1G Switch IP
Related Articles
- ARChitect Processor Configurator: The Power of Configurable Processing At Your Fingertips
- Tutorial: Enhance Your Signal Processing Toolbox with Complex Notation
- This Isn't Your Father's JTAG Anymore
- Reconfiguring Design -> Reconfigurable computing aims at signal processing
Latest Articles
- Design and Development of a Neuromorphic Silicon Suite: PVT Sensing, Stochastic LIF Inference, On-Chip STDP Learning, and Crossbar Programming
- LLM4RTL: Tool-Assisted LLM for RTL Generation
- Towards Delta Aware Training: Efficient DNN Weight Storage for Resource-Constrained FPGAs
- CHERI-D: Secure and efficient inline object ID for CHERI temporal memory safety
- AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing