How to use UML in your SoC hardware/software design: Part 3
Jul 31 2006 (9:30 AM), Embedded.com
Once you have captured the semantics of your SoC application model completely in a neutral form (see Part 2), you are now ready to compile it into software and silicon. Only the semantics of the modeling language matter for translation purposes.
If a class is represented graphically as a box, or even as text, this is of no consequence. The UML is just an accessible graphical front-end for those simple elements.
When you build a 'class' such as CookingStep in a microwave oven, that represents a set of possible cooking steps you might execute, each with a cooking time and power level.
Similarly, when you describe the lifecycle of a cooking step using a state machine, it follows a sequence of states as synchronized by other state machines, external signals, and timers. And in each state, we execute some functions. All of this structure and behavior, for the entire model, is captured as data in the metamodel.
To read the full article, click here
Related Semiconductor IP
- Verification IP for MIPI SoundWire
- 100M/1G/ TSN Endpoint DO-254 IP Core
- Image Signal Processor
- H.265 / HEVC Video Codec
- H.264 / AVC Video Encoder
Related Articles
- How to reuse your IIoT technology investments - now
- How to use snakes to speed up software without slowing down the time-to-market?
- How a voltage glitch attack could cripple your SoC or MCU - and how to securely protect it
- How to manage changing IP in an evolving SoC design
Latest Articles
- Minimum RISC-V: Maximum FPGA Efficiency
- The Era of Vibe Tapeout: Dark Age or Golden Age for Analog Circuit Design?
- Understanding the Power Consumption of Modern High Bandwidth Memory: Experimental Analysis and Modeling Using Real HBM2 DRAM Chips
- BARE-AI: Bit-Flip Attack Resilience in AI Hardware through Built-in Performance Monitors
- RFChipAgent: Multi-Agentic AI Flow for Analog/RF Chip Design