Xelic Announces SONET/SDH Tributary Payload Processor Core Availability for Integration into ASIC or FPGA Networking Applications
Rochester, NY -- March 22, 2005 -- Xelic, Inc., a leading provider of Networking Intellectual Property and Engineering Design Services today announced the immediate availability of their SONET/SDH Tributary Payload Processor Core for product integration.
The Xelic SONET/SDH Tributary Payload Processor Core (XCSTPP12) performs tributary pointer processing, aligns outgoing tributaries and provides tributary path overhead error detection and performance monitoring at an STS-12/STM-4 rate. The XCSTPP12 implements the industry standard telecom bus architecture for interfacing of various signaling and data transfers. Tributary payload processing is provided for any legal mix of VT1.5/TU11, VT2/TU12, VT3, VT6/TU2 or TU3 tributaries using STS-1/VC-3 or VC-4 frame formats.
“The XCSTPP12 adds to Xelic’s growing portfolio of networking cores and provides our customers with the ability to achieve a higher level of integration for switching applications at the tributary level.” said Doug Bush, Director of IP Development at Xelic.
Xelic cores are available under flexible licensing terms and come complete with full documentation and a comprehensive suite of self-checking tests. Core customization and integration services are also available.
Xelic is a privately held Networking Intellectual Property provider and Engineering Services Company. Xelic offers standards based IP for SONET/SDH, Digital Wrapper, Generic Framing Procedure, ATM, and Forward Error Correction applications. Xelic’s Engineering Services include Product Definition, ASIC/FPGA Development, System Design, Board Design, Firmware Design, and full turnkey solutions. Xelic was founded in January of 2001 and is based out of Rochester, NY. For more information about Xelic, please visit www.xelic.com.
Xelic and XCSTPP12 are trademarks of Xelic, Inc. All other trade names, trademarks, and registered trademarks are the property of their respective owners.
The Xelic SONET/SDH Tributary Payload Processor Core (XCSTPP12) performs tributary pointer processing, aligns outgoing tributaries and provides tributary path overhead error detection and performance monitoring at an STS-12/STM-4 rate. The XCSTPP12 implements the industry standard telecom bus architecture for interfacing of various signaling and data transfers. Tributary payload processing is provided for any legal mix of VT1.5/TU11, VT2/TU12, VT3, VT6/TU2 or TU3 tributaries using STS-1/VC-3 or VC-4 frame formats.
“The XCSTPP12 adds to Xelic’s growing portfolio of networking cores and provides our customers with the ability to achieve a higher level of integration for switching applications at the tributary level.” said Doug Bush, Director of IP Development at Xelic.
Xelic cores are available under flexible licensing terms and come complete with full documentation and a comprehensive suite of self-checking tests. Core customization and integration services are also available.
Xelic is a privately held Networking Intellectual Property provider and Engineering Services Company. Xelic offers standards based IP for SONET/SDH, Digital Wrapper, Generic Framing Procedure, ATM, and Forward Error Correction applications. Xelic’s Engineering Services include Product Definition, ASIC/FPGA Development, System Design, Board Design, Firmware Design, and full turnkey solutions. Xelic was founded in January of 2001 and is based out of Rochester, NY. For more information about Xelic, please visit www.xelic.com.
Xelic and XCSTPP12 are trademarks of Xelic, Inc. All other trade names, trademarks, and registered trademarks are the property of their respective owners.
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related News
- Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA
- NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC
- CAST Introduces 100 Gbps TCP/IP Hardware Stack IP Core for High-Performance ASIC and FPGA Designs
- Xelic Announces Family of SONET/SDH Transport Processor Cores for Integration into FPGA or ASIC Networking Applications
Latest News
- GF unveils roadmap to deliver the world’s most advanced FD-SOI platform for Physical AI
- GlobalFoundries marks Dresden expansion milestone, announces next-generation platform for Physical AI
- TSMC September 2026 Revenue Report
- Lattice Collaborates with Arm to Advance Secure, Adaptable AI Data Center Infrastructure
- ZLG Selects CAST CAN XL and TSN IP for Next-Generation Vehicle-Network Development and Test Tools