Synopsys Acquires Verification IP Assets of Qualis Companies

MOUNTAIN VIEW, Calif., April 14, 2003 – Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated circuit (IC) design software, today announced it has acquired the verification Intellectual Property (IP) assets of Qualis, Inc. and its affiliated companies, which perform verification methodology consulting and training. Synopsys plans to integrate Qualis’ Domain Verification Component (DVC™) technology into its DesignWare® Verification IP. In addition, a number of key Qualis personnel will join the Synopsys team, including Janick Bergeron, Qualis, Inc.’s chief technology officer and a recognized industry expert in the field of verification methodology. The purchase price for Qualis’ assets was not disclosed. As a result of the transaction, the Qualis companies will discontinue sale and support of all existing Qualis products and will change their company names.

“Synopsys is committed to building the next-generation unified verification platform,” said Joachim Kunkel, vice president of marketing, Intellectual Property and Design Services, Synopsys, Inc. “As the complexity of on- and off-chip communications protocols continues to increase, verification IP has become an essential part of the testbench. By adding Qualis’ verification technology and engineering talent, Synopsys is accelerating its ability to deliver advanced verification IP to its customers.”

About DesignWare Verification IP
DesignWare Verification IP significantly simplifies the development of testbenches. Verification engineers can take advantage of built-in advanced constrained-random capabilities to generate thousands of transactions and test corner-case behavior with just a few commands. Written in OpenVera™, DesignWare Verification IP has been implemented to be fully functional in Vera, Verilog, VHDL and C-based verification environments. The DesignWare Verification Library is comprised of verification IP for the major components of SoC design. It includes verification IP for complex, standards-based on- and off-chip communications protocols, including the AMBA 2.0 on-chip-bus, PCI, PCI-X 2.0, PCI Express, USB 1.1 and 2.0, Ethernet and IEEE 1394a. It also features more than 8000 memory models as well as simulation views of DesignWare Star IP microprocessor cores.

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com.

Forward Looking Statements
This press release contains forward-looking statements within the meaning of the safe harbor provisions of Section 21E of the Securities Exchange Act of 1934, including statements regarding the expected benefits of the acquisition of Qualis’ Verification IP assets. These statements are based on Synopsys’ current expectations and beliefs. Actual results could differ materially from the results implied by these statements as a result of a number of factors including unforeseen difficulties in integrating Qualis’ products with Synopsys DesignWare verification library, as well as other factors contained in Synopsys’ Quarterly Report on Form 10-Q for the fiscal quarter ended January 31, 2003.

Synopsys and DesignWare are registered trademarks and Open Vera is a trademark of Synopsys, Inc. All other trademarks mentioned in this release are the intellectual property of their respective owners.