Synopsys Delivers Platform Architect Ultra to Enable the Next Wave of AI SoCs
Enables Architecture Exploration for Advanced AI SoCs to Meet Optimal Performance and Power Goals Targeted for Cloud and Edge Applications
MOUNTAIN VIEW, Calif. -- Oct. 15, 2018-- Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of its next-generation architecture exploration, analysis, and design solution, Platform Architect™ Ultra, to address the system challenges of artificial intelligence (AI)-enabled system-on-chips (SoCs). Architects of neural network enabled SoCs need to carefully balance the required convolutional neural network (CNN) throughput against the available power and performance budget that data center or embedded devices can sustain. Platform Architect Ultra flexibly maps CNN algorithms and workloads to explore processing and memory architecture options, enabling architects to analyze, select, optimize, and tune algorithms and architectures for performance and power requirements.
"Designing leading-edge AI chips for our automotive SoCs requires an architecture with the highest performance and energy efficiency," said Takashi Abe, manager at Basis Electronic R&D Division at Denso. "Platform Architect Ultra allows us to quickly assemble an accurate model of our architecture concepts, test these with realistic AI workloads, and efficiently compare hundreds of architecture and IP alternatives, ensuring that our automotive SoCs deliver the absolute optimal performance and power."
"Designers are faced with having to integrate actual software to further validate and substantiate their architecture design assumptions," said Bill Neifert, senior director of Market Development at Arm. "Synopsys Platform Architect Ultra enables our customers to refine their candidate architecture with Arm® Cycle Models to gain a realistic, system-level view of critical functionality to validate SoC performance while executing the software workloads of real AI benchmarks."
Synopsys' Platform Architect Ultra, developed in collaboration with AI SoC leaders, is the next-generation release of Platform Architect, embedding the latest technology to efficiently perform dynamic simulation of multicore architectures. Platform Architect Ultra introduces SMART Tables for context-sensitive data entry and error checking, and SMART Charts for visual root-cause sensitivity analysis of candidate architectures. It also introduces a hierarchical design concept for fast creation and packaging of a design, including ready-to-map workloads, architecture models, and AI reference system, including CNN frameworks such as Caffe and TensorFlow, enabling architects to quickly analyze and optimize a proposed architecture design.
"Through our collaboration with leading AI SoC companies, we know that architecture teams must carefully balance power, performance, and programmability to succeed in this highly competitive market," said Eshel Haritan, vice president of R&D in the Synopsys Verification Group. "Platform Architect Ultra's parallelized exploration, performance, and power optimization capabilities allow designers of neural network architectures and algorithms to quickly find a balanced architecture and eliminate late changes in SoC design."
About Synopsys
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software security and quality solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest security and quality, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related News
- Synopsys Launches Electronics Digital Twin Platform to Accelerate Physical AI System Development
- Synopsys and TSMC Collaborate to Accelerate 2nm Innovation for Advanced SoC Design with Certified Digital and Analog Design Flows
- Mobiveil's PSRAM Controller IP Lets SoC Designers fully Leverage AP Memory's Ultra High Speed (UHS) PSRAM Memory
- Synopsys Announces Industry's First Ultra Ethernet and UALink IP Solutions to Connect Massive AI Accelerator Clusters
Latest News
- StarFive and LECARC Forge Partnership to Co-Develop RISC-V Server CPUs and Seize New Opportunities in the Agentic AI Era
- ASICLAND Selected as SK hynix’s Partner for Next-Gen eSSD Development, Establishing a ‘K-Semiconductor Win-Win’ Model
- onsemi to Acquire Synaptics to Enable the Next Generation of Intelligent Systems for Physical AI
- EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution
- Jim Keller: ‘AI Still Obeys the Old Laws of Compute’