Synopsys plans IP reuse tool

Synopsys plans IP reuse tool
By Richard Goering, EE Times
March 10, 1999 (1:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG19990310S0010

MOUNTAIN VIEW, Calif. — Synopsys Inc. is planning to release tools that facilitate the development and distribution of configurable silicon intellectual property (IP), according to discussions at the recent Intel Developer Forum. The yet to be named tools will leverage the graphical user interface technology that Synopsys uses to develop and deploy its own cores.

Synopsys' PCI core is delivered with a graphical user interface that allows customers to configure the core, and generate synthesis scripts. Synopsys' upcoming NGIO core, announced at the Intel forum, will be created and deployed using the same technology.

"It's like Adobe Acrobat in that there's both a developer side and a reader side," said John Chilton, general manager of the design reuse group at Synopsys, based here. "Any piece of IP built with the developer tool can be instantiated using the reader." He said the "reader" is currently planned for introduction at this month's IP99 Conference, while the "developer" is scheduled to appear at the June Design Automation Conference.