Startup Runs AI in Novel SRAM
Areanna claims 100 TOPS/W in simulation
July 22, 2019
SAN JOSE — In his spare time, an engineer at Tektronix sketched out a novel deep-learning accelerator, and now his two-person startup is the latest example of the groundswell of enthusiasm that deep learning is generating.
Behdad Youssefi defined an SRAM with specialized cells that can handle the matrix multiplication, quantization, storage and other jobs needed for an inference processor. After four years solo work on the concept originally planned as a PhD thesis, he formed startup Areanna with a colleague at Tektronix and a Berkeley professor as an advisor.
In Spice simulations the design delvers more than 100 tera-operations/second/watt when recognizing handwritten digits using 8-bit integer math. Youssefi claims it could beat Google’s TPU in computational density by an order of magnitude.
To read the full article, click here
Related Semiconductor IP
- AP Memory VHM Controller
- High-performance, commercial-grade RISC-V CPU Core IP
- SWI3S Verification IP
- Secure Boot Loader
- Memory Subsystem
Related News
- Startup Slashes SRAM Power With Standard Logic Process
- Israeli AI startup NeuReality raises $35M Series A to bring its novel inferencing chip to the market
- AimFuture, a Leader in Home Appliance NPUs, to Integrate Mesacure Company’s AI Algorithms
- AI Compute Demand Drives 44% YoY Growth for Top 10 Global Fabless IC Firms in 2025
Latest News
- Silvaco Announces Partnership with Dassault Systèmes to Advance First-Time-Right Semiconductor Manufacturing
- Socionext Broadens SoC Roadmap with Intel 18A-P Process Technology
- BrainChip and Neuromorphyx Announce an AKD1500 Embedded Developer Board, Bringing Neuromorphic AI to the Embedded Engineering Community
- M31 Reports Nearly Fourfold Growth in Advanced-Node Royalties as Long-Term Investments Begin to Bear Fruit
- Andes Technology’s D23-SE RISC-V Processor Achieves ISO 26262 ASIL‑B and ASIL‑D Certification for Functional Safety Applications