A new approach could help overcome the speed and lifetime limitations of low-power memory.

• Operation at 0.6 V delivers one of the best reported combinations of low voltage, fast switching, and high endurance.
• Electrode and interface engineering addresses the longstanding speed-endurance dilemma in ferroelectric memory.
• Research published in Nature Communications.

November 3, 2026 -- The College of Engineering at Seoul National University (SNU) announced that a research team led by Professor Min Hyuk Park of the Department of Materials Science and Engineering has developed ferroelectric capacitors that operate rapidly at a low voltage of 0.6 V and retain distinguishable information states without dielectric breakdown after one trillion switching cycles.

The findings address a longstanding challenge in ferroelectric memory: achieving fast operation and a long operating lifetime at the same time. By precisely engineering the interface where the electrode meets the ferroelectric material, the team combined low operating voltage with rapid polarization switching and high cycling stability. The researchers also explored how these properties could be used in next-generation, low-power memory with an architecture similar to DRAM.

The study was conducted in collaboration with researchers at Hanyang University, Pohang Accelerator Laboratory, and Samsung Electronics. The findings were published in Nature Communications.

As AI servers and mobile devices process growing volumes of data, technologies that improve both memory performance and energy efficiency are becoming increasingly important. Energy efficiency is a key concern for high-bandwidth memory (HBM) used in AI servers and for low-power double data rate (LPDDR) memory used in smartphones and other mobile devices.

DRAM is a widely used form of high-speed, volatile memory found in computers, smartphones, and AI servers. It stores information as electrical charge in a capacitor. Because this charge gradually leaks away, it must be replenished periodically to preserve the information. This refresh process affects memory power consumption and operating efficiency.

Ferroelectric memory, by contrast, stores information using polarization, the electrical orientation within a material. The two polarization directions represent the digital states 0 and 1. Its nonvolatile behavior relies on remanent polarization, which remains after the external electric field is removed, and offers a way to reduce the power burden of periodic refresh. Ferroelectrics were also identified as promising materials for next-generation semiconductors in the Semiconductor Future Technology Roadmap announced by Korea's Ministry of Science and ICT in 2023.

The hafnia-zirconia material used in this study, known as HZO, is a ferroelectric formed by combining hafnium oxide and zirconium oxide. Both oxides are already used in semiconductor mass production: hafnium oxide serves as a gate insulator in transistors, while zirconium oxide is used as a dielectric in DRAM capacitors. HZO is highly compatible with existing semiconductor manufacturing processes, and atomic layer deposition can produce uniform films only a few nanometers thick.

Using HZO in next-generation memory with DRAM-class performance, however, requires low voltage, rapid operation, and a long lifetime together. Writing information to ferroelectric memory requires reversing the polarization direction. Faster polarization switching generally requires a higher voltage, but a higher voltage can place greater stress on the device and shorten its cycling lifetime. This difficulty in improving both switching speed and cycling endurance is known as the speed-endurance dilemma.

Reducing the film thickness alone also has limits as a way to lower the operating voltage. As the film becomes extremely thin, the electric field required for polarization switching and the influence of the electrode interfaces become more significant. Thinning the film therefore does not necessarily reduce the operating voltage sufficiently.

Conceptual illustration of the ferroelectric capacitor and its proposed memory application. From left: the electrode and interface structure; the depolarization field assisting the initial stage of polarization switching; and the proposed common-plate ferroelectric RAM (CP-FeRAM) architecture. The memory architecture is proposed and evaluated through circuit simulations. Conceptual illustration generated with ChatGPT.

To address these challenges, the team focused on the interface between the electrode and the ferroelectric. Using atomic layer deposition, the researchers controlled the crystal orientation and surface properties of titanium nitride (TiN) electrodes and suppressed interfacial oxidation to form a thin, uniform interfacial layer. This reduced voltage loss at the interface and created conditions that support uniform polarization switching.

As a result, the team achieved polarization switching at just 0.6 V in HZO capacitors with a film thickness of 5 nm. Even at this low voltage, the devices produced a clear polarization signal sufficient to distinguish different information states.

In the test devices, the time required to switch half of the total polarization was approximately 40 ns at 0.6 V and 8 ns at 1 V. A nanosecond is one billionth of a second. At both voltages, no dielectric breakdown was observed after one trillion switching cycles, and the two polarization states remained distinguishable. With endurance defined by a polarization reduction of less than 20%, the devices reached 600 billion cycles at 0.6 V and one trillion cycles at 1 V. The researchers said that, compared with previously reported ferroelectric capacitors, the devices achieved one of the best reported combinations of operating voltage, switching speed, and endurance.

The team attributed this performance to a reduction in voltage loss through electrode and interface engineering, together with the use of an internal electric field to assist polarization switching. The depolarization field inside a ferroelectric can normally weaken remanent polarization and impair information retention. The researchers found, however, that during the initial stage of polarization reversal, this field can help reduce the external voltage needed to initiate switching.

A model incorporating electrode and interface properties explained this mechanism and identified a design approach for obtaining a sufficient polarization signal at low voltage even in very thin ferroelectric films. The team also found that switching became faster as the device area decreased. Based on their measurements, they predicted that smaller, nanoscale devices could achieve nanosecond polarization switching at low voltage, suggesting a potential route to the high-speed operation required for DRAM-class memory.

The team also examined how these properties could be incorporated into a memory architecture. Based on the one-transistor, one-capacitor (1T-1C) cell used in DRAM, the researchers proposed common-plate ferroelectric RAM (CP-FeRAM), which uses remanent polarization to store and read information. In this design, the voltage of the common electrode shared by multiple memory cells is held constant.

Circuit simulations based on the measured polarization characteristics indicated that information could be distinguished using remanent polarization even after the stored charge had decreased. The researchers also tested a capacitor array with a shared common electrode. The devices operated uniformly, and no clear polarization loss was observed after repeated switching of neighboring devices.

The study combines low operating voltage, fast polarization switching, and high endurance, and connects these device properties to a memory architecture similar to DRAM. Information storage based on remanent polarization could provide a foundation for next-generation memory with a reduced need to replenish charge through periodic refresh.

The approach could also support higher memory density. As memory cells become smaller, the electrical signals used to distinguish information states also decrease, making the stored information harder to read. A large remanent polarization could provide a sufficient readout signal even with smaller capacitors, potentially allowing more memory cells to fit within the same area.

The researchers expect that combining HZO's compatibility with established semiconductor materials and processes with the low-voltage, high-speed, and high-endurance characteristics demonstrated here could broaden its prospects for memory applications. They anticipate that the proposed design and operating principles could also be applied to low-power embedded memory integrated with computing circuits, as well as to high-density memory targeting DRAM-class operation.

'Developing memory that operates quickly at low voltage and can withstand repeated use over a long period is an important challenge,' said Professor Min Hyuk Park, who led the study. 'The significance of this work is that electrode and interface engineering enabled us to achieve these three characteristics together and offer a solution to the longstanding tradeoff between switching speed and lifetime in ferroelectric memory.'

'HZO is a promising ferroelectric that can be developed using oxide materials and process technologies already established in the semiconductor industry,' he added. 'We expect the interface design and polarization-switching principles presented in this study to contribute to the development of low-power, high-density memory technologies.'

First author Dr. Geun Hyeong Park earned his Ph.D. in Materials Science and Engineering through SNU's combined master's and doctoral program and is currently a postdoctoral researcher at SNU's Inter-University Semiconductor Research Center. Building on his experience in memory-device architecture design and analysis of operating characteristics, he plans to continue developing low-power, high-performance memory devices to improve the energy efficiency and integration density of AI semiconductors.

This research was supported by Korea's Ministry of Science and ICT, the National Research Foundation of Korea, and Samsung Electronics.

Article details

Paper: Resolving the Kay–Dunn limit and the speed–endurance dilemma in ferroelectric Hf0.5Zr0.5O2 for DRAM-class sub-volt capacitors

Journal: Nature Communications

DOI: https://doi.org/10.1038/s41467-026-78705-4

Media contacts

Geun Hyeong Park, Ph.D.

Postdoctoral Researcher
Inter-University Semiconductor Research Center
Seoul National University
geunhyeong.park@snu.ac.kr
Telephone: +82 10 3691 1776

Research group: Nanoelectronic and Energy Materials Laboratory, Department of Materials Science and Engineering, Seoul National University