Semidynamics: The landscape for RISC-V and AI compute

An interview with Semidynamics CEO Roger Espasa.

By David Harold, Jon Peddie Research (February 24, 2025)

Semidynamics CEO Roger Espasa discusses the company’s high-performance, configurable RISC-V IP, which emphasizes memory bandwidth and customization for AI and HPC. He highlights their Gazzillion Misses latency-handling IP, integrated tensor units, and focus on real-world performance over benchmarks. Espasa sees RISC-V gaining ground on Arm, balancing standardization with flexibility, and predicts a shift in AI and chiplet adoption.

Semidynamics CEO Roger Espasa discusses the company’s high-performance, configurable RISC-V IP, which emphasizes memory bandwidth and customization for AI and HPC. He highlights their Gazzillion Misses latency-handling IP, integrated tensor units, and focus on real-world performance over benchmarks. Espasa sees RISC-V gaining ground on Arm, balancing standardization with flexibility, and predicts a shift in AI and chiplet adoption.

Its solutions range from stand-alone CPU cores to all-in-one designs (including NPUs) built around tensor, vector, and CPU combinations. One of Semidynamics’ key differentiators is its emphasis on memory bandwidth and customization. Features like the Gazzillion TLB (translation lookaside buffer) and configurable memory subsystems allow designers to adapt processors to specific workloads, particularly for AI and data-intensive applications.

In an interview with JPR’s David Harold, Semidynamics CEO Roger Espasa talks about the company’s RISC-V IP and what he envisions for RISC-V’s future.

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